Buffer placement in distributed RC-tree networks for minimal Elmore delay

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1990, Pages 865-868

  van Ginneken, Lukas P P P ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY--COMPUTATIONAL COMPLEXITY; COMPUTER PROGRAMMING--ALGORITHMS; INTEGRATED CIRCUITS, CMOS--COMPUTER AIDED DESIGN;

ALGORITHM COMPLEXITY; BUFFER PLACEMENT; DISTRIBUTED RC TREE NETWORK; FANOUT TREE; HIERARCHICAL ALGORITHM; IC PROPAGATION DELAY;

INTEGRATED CIRCUITS, VLSI;

EID: 0025594311     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)