Perfect-balance planar clock routing with minimal path-length

IEEE/ACM International Conference on Computer-Aided Design

Volumn , Issue , 1992, Pages 473-476

  Zhu, Qing ^a   Dai, Wayne Wei Ming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; DIGITAL CIRCUITS; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; REMOTE CONTROL; TREES (MATHEMATICS); VLSI CIRCUITS;

CLOCK NET; CLOCK PHASE DELAY; CLOCK TERMINAL; EQUAL PATH LENGTH; INDUSTRIAL BENCHMARKS; PLANAR CLOCK ROUTING; PLANAR CLOCK TREE; REMOTE CONTROL DELAY;

INTEGRATED CIRCUIT LAYOUT;

EID: 0026987101     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.1992.279325     Document Type: Conference Paper

References (6)