A 200-MHz 64-b Dual-Issue CMOS Microprocessor

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 11, 1992, Pages 1555-1567

  Dobberpuhl, Daniel W ^a   Witek, Richard T ^a   Allmon, Randy ^a   Anglin, Robert ^a   Bertucci, David ^a   Britton, Sharon ^a   Chao, Linda ^a   Conrad, Robert A ^a   Dever, Daniel E ^a   Gieseke, Bruce ^a   Hassoun, Soha M N ^a   Hoeppner, Gregory W ^a   Kuchler, Kathryn ^a   Ladd, Maureen ^a   Leary, Burton M ^a   Madden, Liam ^a   Mclellan, Edward J ^a   Meyer, Derrick R ^a   Montanaro, James ^a   Priore, Donald A ^a   Rajagopalan, Vidya ^a   Samudrala, Sridhar ^a   Santhanam, Sribalan ^a   more..

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; EMITTER COUPLED LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS; TRANSISTOR TRANSISTOR LOGIC CIRCUITS; VLSI CIRCUITS;

ALPHA ARCHITECTURE; CACHE MEMORY; CMOS MICROPROCESSOR; FULLY-PIPELINED FLOATING-POINT UNIT; VLSI CPU;

MICROPROCESSOR CHIPS;

EID: 0026955423     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.165336     Document Type: Article

References (5)

1. Alpha Architecture Handbook, EC-H1689-10, Digital Equipment Corp., 1992.
2. J. Yuan and C. Svensson, “Highspeed CMOS circuit techniques,” IEEE J. Solid-State Circuits, vol. SC-24, no. 1, pp. 62-70, Feb. 1989.
3. R. Conrad et al., “A 50 MIPS (peak) 32/64-b microprocessor,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 76-77.
4. J. Sklansky, “Conditional-sum addition logic,” IRE Trans. Electron. Comput., vol. EC-9, pp. 226-231, 1960.
5. H. Lee et al., “An experimental 1 Mb CMOS SRAM with configurable organization and operation,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 180-181.