메뉴 건너뛰기




Volumn 24, Issue 1, 1989, Pages 62-70

High-Speed CMOS Circuit Technique

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTERS, DIGITAL--ADDERS; ELECTRONIC CIRCUITS, TIMING; INTEGRATED CIRCUITS, DIGITAL; SEMICONDUCTOR DEVICES, MOS;

EID: 0024611252     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.16303     Document Type: Article
Times cited : (534)

References (23)
  • 1
    • 0020734746 scopus 로고
    • VLSI physics
    • C. Svensson, “VLSI physics,” Integration, vol. 1, pp. 3-19. 1983.
    • (1983) Integration , vol.1 , pp. 3-19
    • Svensson, C.1
  • 2
    • 0016506999 scopus 로고
    • Physical limits in digital electronics
    • R. W. Keyes, “Physical limits in digital electronics,” Proc. IEEE, vol. 63, p 740, 1975.
    • (1975) Proc. IEEE , vol.63 , pp. 740
    • Keyes, R.W.1
  • 3
    • 0018480027 scopus 로고
    • Characteristics and limitation of scaled-down MOSFETs due to twodimensional field effect
    • H. Masuda, M. Nakai, and M. Kubo, “Characteristics and limitation of scaled-down MOSFETs due to twodimensional field effect,” IEEE Trans, Electron Devices. vol. ED-26, pp. 980-986. 1979.
    • (1979) IEEE Trans, Electron Devices. , vol.ED-26 , pp. 980-986
    • Masuda, H.1    Nakai, M.2    Kubo, M.3
  • 4
    • 0001951703 scopus 로고
    • System timing
    • C. Mead and L. Conwav. Eds. Reading. MA: Addison-Wesiev, ch. 7
    • C. Seitz, “System timing,” in Introduction to VLSI Systems, C. Mead and L. Conwav. Eds. Reading. MA: Addison-Wesiev. 1980. ch. 7.
    • (1980) Introduction to VLSI Systems
    • Seitz, C.1
  • 7
    • 0020311919 scopus 로고
    • Electrical design of BELLMAC-32A microprocessor.
    • M. Shop. “Electrical design of BELLMAC-32A microprocessor.” in Proc. IEEE Int. Conf. Circuits Comput., 1982, pp. 112-1is.
    • (1982) Proc. IEEE Int. Conf. Circuits Comput. , pp. 112-1is
    • Shop, M.1
  • 8
    • 0020776123 scopus 로고
    • NORA: A racefree dynamic CMOS technique for pipelined logic structures
    • N. Goncalves and H. j. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” It Eh J. Solid-State Circuits, vol. SC-18, pp. 261-266. 1983.
    • (1983) It Eh J. Solid-State Circuits , vol.SC-18 , pp. 261-266
    • Goncalves, N.1    De Man, H.J.2
  • 9
    • 0023436314 scopus 로고
    • A true single phase clock dvnamic CMOS circuit technique.
    • Y. Ji-ren. I. Karlsson, and C. Svensson, “A true single phase clock dvnamic CMOS circuit technique.” IEEE J. Solid-State Circuits. vol. SC-22, pp. 899-901. 1987.
    • (1980) IEEE J. Solid-State Circuits. , vol.SC-22 , pp. 899-901
    • Ji-ren, Y.1    Karlsson, I.2    Svensson, C.3
  • 10
    • 85037134942 scopus 로고    scopus 로고
    • Layout design rules for 3.0 am P-well CMOS
    • VTI Technology Inc., San Jose, CA.
    • “Layout design rules for 3.0 am P-well CMOS,“ VTI Technology Inc., San Jose, CA.
  • 11
    • 0024123374 scopus 로고    scopus 로고
    • True single phase clock dynamic CMOS circuit technique.
    • I. Karlsson. “True single phase clock dynamic CMOS circuit technique.” in Proc. 1988 lE'EE Ini. Srmp. Circuits Svst., vol. 1. pp. 475-478.
    • Proc. 1988 lE'EE Ini. Srmp. Circuits Svst. , vol.1 , pp. 475-478
    • Karlsson, I.1
  • 12
    • 0022686204 scopus 로고
    • Signal resvnchronization in VLSI systems.
    • C, Svensson, “Signal resvnchronization in VLSI systems.” Integration, vol. 4, pp. 75-80. 1986.
    • (1986) Integration , vol.4 , pp. 75-80
    • Svensson, C.1
  • 13
    • 0001893927 scopus 로고
    • Performance-oriented synthesis of large-scale domino CMOS circuits
    • G. De Mieheii, “Performance-oriented synthesis of large-scale domino CMOS circuits,” IEEE Trans. Computer-Aided Des., vol. CAD-6, pp. 751-765, 1987.
    • (1987) IEEE Trans. Computer-Aided Des. , vol.CAD-6 , pp. 751-765
    • De Mieheii, G.1
  • 14
    • 0023401701 scopus 로고
    • A comparison of CMOS circuit techniques; Differential casecode voltage switch logic versus conventional Jogic.
    • K. M. Chu and D. L. Pulfrey. “A comparison of CMOS circuit techniques; Differential casecode voltage switch logic versus conventional Jogic.” IEEE J. Solid-State Circuits, vol. SC-22, pp. 528-532. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 528-532
    • Chu, K.M.1    Pulfrey, D.L.2
  • 15
    • 84941427485 scopus 로고
    • Optimization of device area and overall delay for CMOS V] SI designs
    • pp. f v3
    • E. Tie “Optimization of device area and overall delay for CMOS V] SI designs,” Proc. IEEE. vol. 72. pp. f v3 1984.
    • (1984) Proc. IEEE. , vol.72
    • Tie, E.1
  • 16
    • 84941453315 scopus 로고    scopus 로고
    • Macromodelin nd ntimba-tion o'di,>, tat MOS VLSI circuits.
    • M. D SUtMir and L. A. Glasser, “Macromodelin nd ntimba-tion o'di,>, tat MOS VLSI circuits.” IEEE Tran, computer-Aided., vol. TAO-5, pp. 659-678
    • IEEE Tran, computer-Aided. , vol.TAO-5 , pp. 659-678
    • SUtMir, M.D.1    Glasser, L.A.2
  • 17
    • 0022135064 scopus 로고
    • FET scaling in domino CMOS gates
    • M. Shoji, “FET scaling in domino CMOS gates,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1067-1071, 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 1067-1071
    • Shoji, M.1
  • 18
    • 0023211132 scopus 로고
    • Aesop: A tool for automated transistor sizing
    • paper 7.1
    • K. S. Hcdlund, “Aesop: A tool for automated transistor sizing,” in Proc. 24th ACM/IEEE Design Automation Conf., 1987, paper 7.1, pp. 114-120.
    • (1987) Proc. 24th ACM/IEEE Design Automation Conf. , pp. 114-120
    • Hcdlund, K.S.1
  • 20
    • 0024124575 scopus 로고    scopus 로고
    • CMOS circuit speed optimization based on switch level simulation
    • J. Yuan and C. Svensson, “CMOS circuit speed optimization based on switch level simulation,” in Proc. 1988 IEEE Int. Svmp. Circuits Syst., vol. 3, pp. 2109-2112.
    • Proc. 1988 IEEE Int. Svmp. Circuits Syst. , vol.3 , pp. 2109-2112
    • Yuan, J.1    Svensson, C.2
  • 21
    • 0023312489 scopus 로고
    • Fully dynamic switch level simulation of CMOS circuits
    • R. Sundblad and C. Svensson, “Fully dynamic switch level simulation of CMOS circuits,” IEEE Trans. Computer-Aided Des., vol. CAD-6, pp. 282-289, 1987.
    • (1987) IEEE Trans. Computer-Aided Des. , vol.CAD-6 , pp. 282-289
    • Sundblad, R.1    Svensson, C.2
  • 23
    • 0000682349 scopus 로고
    • A switch-level timing verifier for digital MOS VLSI
    • J. K. Ousterhout, “A switch-level timing verifier for digital MOS VLSI,” IEEE Trans. Computer-Aided Des., vol. CAD-4, pp. 336-349, 1985.
    • (1985) IEEE Trans. Computer-Aided Des. , vol.CAD-4 , pp. 336-349
    • Ousterhout, J.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.