Buffer insertion and sizing under process variations for low power clock distribution

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 491-496

  Xi, Joe G ^a   Dai, Wayne W M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; ELECTRIC LOSSES; ELECTRIC WIRE; ELECTRIC WIRING; MOS DEVICES; OPTIMIZATION; SHORT CIRCUIT CURRENTS;

BUFFER INSERTION; CLOCK DISTRIBUTION; DEVICE PARAMETER VARIATIONS; POWER DISSIPATION;

DIGITAL INTEGRATED CIRCUITS;

EID: 0029223026     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217576     Document Type: Conference Paper

References (13)