-
1
-
-
0022953369
-
A symmetric clock-distribution tree and optimized high speed interconnections for rereduced clock skew in ULSI and WSI circuits
-
H. B. Bakoglu, J. T. Walker, and J. D. Meindl, “A symmetric clock-distribution tree and optimized high speed interconnections for rereduced clock skew in ULSI and WSI circuits,” in IEEE Int. Conf. Computer Design: VLSI in Computers, 1986, pp. 118-122.
-
(1986)
IEEE Int. Conf. Computer Design: VLSI in Computers
, pp. 118-122
-
-
Bakoglu, H.B.1
Walker, J.T.2
Meindl, J.D.3
-
2
-
-
0025470204
-
Computing signal delay in general rc network by tree/link partitioning
-
Aug.
-
P. K. Chan and K. Karplus, “Computing signal delay in general rc network by tree/link partitioning,” IEEE Trans. Computer-Aided Design, vol. 9, pp. 898–-902, Aug. 1990.
-
(1990)
IEEE Trans. Computer-Aided Design
, vol.9
, pp. 898-902
-
-
Chan, P.K.1
Karplus, K.2
-
5
-
-
34748823693
-
The transient response of damped linear networks with particular regard to wide band amplifiers
-
W. C. Elmore, “The transient response of damped linear networks with particular regard to wide band amplifiers,” J. Appl. Phys., vol. 19, pp. 55–63, 1948.
-
(1948)
J. Appl. Phys.
, vol.19
, pp. 55-63
-
-
Elmore, W.C.1
-
6
-
-
0025464163
-
Clock skew optimization
-
July
-
J. P. Fishbum, “Clock skew optimization,” IEEE Trans. Computers, vol. 39, pp. 945–951, July 1990.
-
(1990)
IEEE Trans. Computers
, vol.39
, pp. 945-951
-
-
Fishbum, J.P.1
-
7
-
-
0020314030
-
Synchronous large systolic arrays
-
A. L. Fisher and H. T. Kung, “Synchronous large systolic arrays,” in Proc. SPIE, 1982, pp. 44–52.
-
(1982)
Proc. SPIE
, pp. 44-52
-
-
Fisher, A.L.1
Kung, H.T.2
-
8
-
-
0025546578
-
Clock routing for high-performance IC’s
-
M. A. B. Jackson, A. Srinivasan, and E. S. Kuh, “Clock routing for high-performance IC’s,” in Proc. Design Automation Conf., 1990, pp. 573–579.
-
(1990)
Proc. Design Automation Conf.
, pp. 573-579
-
-
Jackson, M.A.B.1
Srinivasan, A.2
Kuh, E.S.3
-
9
-
-
0026175375
-
High-performance clock routing based on recursive geometric matching
-
A. Kahng, J. Cong, and G. Robins, “High-performance clock routing based on recursive geometric matching,” in Proc. Design Automation Conf., 1991, pp. 322–327.
-
(1991)
Proc. Design Automation Conf.
, pp. 322-327
-
-
Kahng, A.1
Cong, J.2
Robins, G.3
-
10
-
-
0020303836
-
Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors
-
S. Y. Kung and R. J. Gal-Ezer, “Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors,” in Proc. SPIE. 1982, pp. 53–65.
-
(1982)
Proc. SPIE
, pp. 53-65
-
-
Kung, S.Y.1
Gal-Ezer, R.J.2
-
11
-
-
0020504458
-
Optimizing synchronous circuitry by retiming
-
C. E. Leiserson, F. M. Rose, and J. B. Saxe, “Optimizing synchronous circuitry by retiming,” in Proc. Third Caltech Conf., 1983, pp. 87–116.
-
(1983)
Proc. Third Caltech Conf.
, pp. 87-116
-
-
Leiserson, C.E.1
Rose, F.M.2
Saxe, J.B.3
-
12
-
-
0026175402
-
RICE: Rapid interconnect circuit evaluator
-
C. L. Ratzlaff, N. Gopal, and L. T. Pillage, “RICE: Rapid interconnect circuit evaluator,” in Proc. Design Automation Conf., 1991, pp. 555–560.
-
(1991)
Proc. Design Automation Conf.
, pp. 555-560
-
-
Ratzlaff, C.L.1
Gopal, N.2
Pillage, L.T.3
-
13
-
-
0020778211
-
Signal delay in rc tree networks
-
J. Rubinstein, P. Penfield, and M. A. Horowitz, “Signal delay in rc tree networks,” IEEE Trans. Computer-Aided Design, vol. CAD-2 pp. 202–211, 1983.
-
(1983)
IEEE Trans. Computer-Aided Design
, vol.CAD-2
, pp. 202-211
-
-
Rubinstein, J.1
Penfield, P.2
Horowitz, M.A.3
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