Power optimal buffered clock tree design

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 497-502

  Vittal, Ashok ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC LOSSES; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; MATHEMATICAL MODELS; TIMING CIRCUITS; TREES (MATHEMATICS); VLSI CIRCUITS;

CLOCK NETWORK DESIGN; CLOCK ROUTING; POWER DISSIPATION; POWER MINIMIZATION PROBLEM; STEINER TREE PROBLEM;

ELECTRIC NETWORK SYNTHESIS;

EID: 0029214073     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217577     Document Type: Conference Paper

References (25)