A concept of analog-digital merged circuit architecture for future VLSI's

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E79-A, Issue 2, 1996, Pages 145-156

  Iwata, Atsushi ^a   Nagata, Makoto ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

Pulse width modulation (PWM); PWM adder; PWM signal converter; Switched current integrator

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; INTEGRATED CIRCUIT LAYOUT; PULSE WIDTH MODULATION;

MERGED CIRCUIT ARCHITECTURE; SWITCHED CURRENT INTEGRATOR;

VLSI CIRCUITS;

EID: 0030086540     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (29)

1. T. Sugibayashi, I. Naritake, S. Utsugi, K. Shibahara, R. Oikawa, H. Mori, S. Iwao, T. Murotani, K. Koyama, S. Fukuzawa, T. Itani, K. Kasama, T. Okuda, S. Ohya, and M. Ogawa, "A 1 Gb DRAM for file applications," Digest of ISSCC95, pp. 254-255, 1995.
2. K. Suzuki, M. Yamashina, T. Nakayama, M. Izumikawa, M. Nomura, H. Igura, H. Heiuchi, J. Goto, T. Inoue, Y. Koseki, H. Abiko, K. Okabe, A. Ono, Y. Yano, and H. Yamada, "A 500 MHz 32 b 0.4 μm CMOS RISC processor LSI," Digest of ISSCC94, pp. 214-215, 1994.
3. B. Del Signore, D. Kerth, N. Sooch, and E. Awanson, "A monolithic 20-b delta-sigma A/D converter," IEEE J. of Solid-State Circuits, vol. 25, no. 6, pp. 1311-1317, 1990.
4. M. Soda, H. Tezuka, F. Sato, T. Hashimoto, S. Nakamura, T. Tatsumi, T. Suzaki, and T. Tashiro, "Si-analog ICs for 20 Gb/s optical receiver," Digest of ISSCC94, pp. 170-171, 1994.
5. S. Wong and A. Salama, "Impact of scaling on MOS analog performance," IEEE J. of Solid-State Circuits, vol. SC-18, no. 1, pp. 106-114, 1983.
6. E. Sano, T. Tsukahara, and A. Iwata, "Performance limits of mixed analog/digital circuits with scaled MOSFETs," IEEE J. of Solid-State Circuits, vol. SC-23, no. 4, pp. 942-949, 1988.
7. R. Widlar, "Design techniques of monolithic operational amplifier," IEEE J. of Solid-State Circuits, vol. SC-4, no. 8, pp. 184-191, 1969.
8. P. Gray and R. Meyer, "MOS operational amplifier design-A tutorial," IEEE J. of Solid-State Circuits, vol. SC-17, no. 12, pp. 969-983, 1982.
9. A. Abidi, "Low-power radio-frequency IC's for portable communications," Proc. of IEEE, vol. 83, no. 4, pp. 544-569, 1995.
10. J. McCreary and P. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques - part II," IEEE J. of Solid-State Circuits, vol. SC-10, no. 6, pp. 371-379, 1975.
11. K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, "Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators," IEEE Trans. ASSP, vol. 36, no. 12, pp. 1899-1905, 1988.
12. Y. Matsuya and J. Yamada, "1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping," IEEE J. of Solid-State Circuits, vol. SC-2/, no. 12, pp. 1524-1530, 1994.
13. B. Hosticka, R. Brodersen, and P. Gray, "MOS sampled data recursive filters using switched capacitor integrators," IEEE J. of Solid-State Circuits, vol. SC-12, no. 6, pp. 600-608, 1977.
14. A. Iwata, H. Kikuchi, K. Uchimura, A. Morino, and M. Nakajima, "A single-chip CODEC with switched-capacitor filters," IEEE J. of Solid-State Circuits, vol. SC-16, no. 4, pp. 315-321, 1981.
15. Y. Tsividis, "Integrated continuous-time filter design - an overview," IEEE J. of Solid State Circuits, vol. SC29, no. 3, pp. 166-176, 1994.
16. J. Alvarez, H. Sanchez, G. Gerosa, and R. Countryman, "A wide-bandwidth low-voltage PLL for powerPC microprocessors," IEEE J. of Solid State Circuits, vol. SC30, no. 4, pp. 383-391, 1995.
17. T. Lee, K. Donnelly, J. Ho, M. Zerbe, and T. Ishikawa, "A 2.5V delay-locked loop for an 18 Mb 500 MB/s DRAM," Digest of ISSCC94, pp. 300-301, 1994.
18. K. Fukuda, S. Maeda, T. Tsukada, and T. Matsuura, "Substrate noise reduction using active guard band filters in mixed-signal integrated circuits," 1995 Symp. on VLSI Circuits, pp. 33-34, 1995.
19. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, "A 3.8-ns CMOS 16×16-b multiplier using complementary pass-transistor logic," IEEE J. of Solid-State Circuits, vol. SC-25, no. 2, pp. 388-395, 1990.
20. H. Yamauchi, H. Akamatsu, and T. Fujita, "An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's," IEEE J. of Solid-State Circuits, vol. SC-30, no. 4, pp. 423-431, 1995.
21. A. Kramer, J. Denker, S. Avery, G. Dickson, and T. Wik, "Adiabatic computing with the 2N-2N2D logic family," 1994 Symp. on VLSI Circuits, pp. 25-26, 1994.
22. T. Ohmi and T. Shibata, "The concept of four-terminal devices and its significance in the implementation of intelligent integrated circuits," IEICE Trans. Electron, vol. E77-C, no. 7, pp. 1032-1041, 1994.
23. T. Ohmi, "Integrating intelligence on silicon electronic systems," 1995 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-2, 1995.
24. T. Morie and Y. Amemiya, "An all-analog expandable neural network LSI with on-chip backpropagation learning," IEEE J. of Solid-State Circuits, vol. SC-29, no. 9, pp. 1086-1093, 1994.
25. C. Mead and M. Mahowald, "A silicon model of early visual processing," Neural Networks, vol. 1, pp. 91-97, 1988.
26. A. Murray, D. Del Corso, and L. Tarassenko, "Pulse-stream VLSI neural networks mixing analog and digital techniques," IEEE Trans. on Neural Networks, vol. 2, no. 2, pp. 193-204, 1991.
27. K. Nogami and A. El Gamal, "A CMOS 160 Mb/s phase modulation I/O interface circuits," ISSCC Digest of Technical Papers, pp. 108-109, Feb. 1994.
28. T. Yamauchi, Y. Morooka, and H. Ozaki, "A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory," 1995 Symp. on VLSI Circuits, pp. 27-28, 1995.
29. A. Iwata and I. Hayashi, "Optical interconnections as a new LSI technology," IEICE Trans. Electron, vol. E76-C, no. 1, pp. 90-99, 1993.