메뉴 건너뛰기




Volumn 23, Issue 4, 1988, Pages 942-949

Performance Limits of Mixed Analog/Digital Circuits With Scaled Mosfet'S

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL, ELECTRIC VARIABLES -- VOLTAGE; ELECTRIC FIELDS; SEMICONDUCTOR DEVICES, MOSFET -- PERFORMANCE;

EID: 0024056632     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.345     Document Type: Article
Times cited : (10)

References (28)
  • 1
    • 0016506999 scopus 로고
    • “Physical limits in digital electronics,”
    • R. W. Keyes, “Physical limits in digital electronics,” Proc. IEEE, vol. 63, pp. 740–767, 1975.
    • (1975) Proc. IEEE , vol.63 , pp. 740-767
    • Keyes, R.W.1
  • 2
    • 0016116644 scopus 로고
    • “Design of ion implanted MOSFET's with very small physical dimensions,”
    • R. H. Dennard et al., “Design of ion implanted MOSFET's with very small physical dimensions,” IEEE J. Solid-state Circuits, vol. SC-9, pp. 256–266, 1974.
    • (1974) IEEE J. Solid-state Circuits , vol.SC-9 , pp. 256-266
    • Dennard, R.H.1
  • 3
    • 0019075967 scopus 로고
    • “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,”
    • P. K. Chatterjee et al., “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220–223, 1980.
    • (1980) IEEE Electron Device Lett. , vol.EDL-1 , pp. 220-223
    • Chatterjee, P.K.1
  • 4
    • 0020832969 scopus 로고
    • “A reexamination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI,”
    • H. Shichijo, “A reexamination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI,” Solid-state Electron., vol. 26, pp. 969–986, 1983.
    • (1983) Solid-state Electron. , vol.26 , pp. 969-986
    • Shichijo, H.1
  • 5
    • 85038061827 scopus 로고
    • “Circuit scaling limits for ultra-large-scale integration,”
    • Feb.
    • J. D. Meindl et al., “Circuit scaling limits for ultra-large-scale integration,” in ISSCC Dig. Tech. Papers, Feb. 1981, pp. 36–37.
    • (1981) ISSCC Dig. Tech. Papers , pp. 36-37
    • Meindl, J.D.1
  • 6
    • 84939365158 scopus 로고
    • “Performance limits of CMOS ULSI,”
    • J. R. Pfiester et al., “Performance limits of CMOS ULSI,” IEEE Trans. Electron Devices, vol. ED-32, pp. 333–343, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 333-343
    • Pfiester, J.R.1
  • 8
    • 84945713874 scopus 로고
    • “Physical limits of VLSI dRAM's,”
    • L. L. Lewyn and J. D. Meindl, “Physical limits of VLSI dRAM's,” IEEE Trans. Electron Devices, vol. ED-32, pp. 311–321, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 311-321
    • Lewyn, L.L.1    Meindl, J.D.2
  • 9
    • 0020705925 scopus 로고
    • “Impact of scaling on MOS analog performances,”
    • Feb.
    • S. Wong and C. A. T. Salama, “Impact of scaling on MOS analog performances,” IEEE J. Solid-state Circuits, vol. SC-18, pp. 106–114, Feb. 1983.
    • (1983) IEEE J. Solid-state Circuits , vol.SC-18 , pp. 106-114
    • Wong, S.1    Salama, C.A.T.2
  • 10
    • 0023535349 scopus 로고
    • “Device design requirements for MOS analog circuits,”
    • May
    • C. G. Sodini et al., “Device design requirements for MOS analog circuits,” in Proc. Symp. VLSI Circuits, May 1987, pp. 57–60.
    • (1987) Proc. Symp. VLSI Circuits , pp. 57-60
    • Sodini, C.G.1
  • 11
    • 84913283199 scopus 로고
    • “Signal processing using MOSVLSI technology,”
    • N. G. Einspruch, Ed. New York: Academic
    • R. W. Brodersen, “Signal processing using MOSVLSI technology,” in VLSI Electronics: Microstructure Science, N. G. Einspruch, Ed. New York: Academic, 1981.
    • (1981) VLSI Electronics: Microstructure Science
    • Brodersen, R.W.1
  • 12
    • 0022917012 scopus 로고
    • “VLSI architecture for an adaptive equalizer in ISDN line termination,”
    • Apr.
    • M. Ishikawa et al., “VLSI architecture for an adaptive equalizer in ISDN line termination,” in ICASSP Proc, Apr. 1986, pp. 1525–1528.
    • (1986) ICASSP Proc , pp. 1525-1528
    • Ishikawa, M.1
  • 13
    • 84941468760 scopus 로고
    • “CMOS device model for accurate circuit simulation,”
    • ‘in Japanese’; ‘English translation to be published in Electron. Commun. in Japan, Scripta Technica, Inc.’.
    • E. Sano and T. Kimura, “CMOS device model for accurate circuit simulation,” Trans. IECE Japan, vol. J70-C, pp. 135–142, 1987 ‘in Japanese’; ‘English translation to be published in Electron. Commun. in Japan, Scripta Technica, Inc.’.
    • (1987) Trans. IECE Japan , vol.J70-C , pp. 135-142
    • Sano, E.1    Kimura, T.2
  • 15
    • 84944378023 scopus 로고
    • “A parametric short-channel MOS transistor model for subthreshold and strong inversion current,”
    • T. Grotjohn and B. Hoefflinger, “A parametric short-channel MOS transistor model for subthreshold and strong inversion current,” IEEE Trans. Electron Devices, vol. ED-31, pp. 234–246, 1984.
    • (1984) IEEE Trans. Electron Devices , vol.ED-31 , pp. 234-246
    • Grotjohn, T.1    Hoefflinger, B.2
  • 16
    • 0020928675 scopus 로고
    • “A low-frequency noise analysis using twodimensional numerical analysis method,”
    • E. Sano et al., “A low-frequency noise analysis using twodimensional numerical analysis method,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1699–1704, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 1699-1704
    • Sano, E.1
  • 17
    • 84916389355 scopus 로고
    • “Large-signal analysis of a silicon Read diode oscillator,”
    • D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a silicon Read diode oscillator,” IEEE Trans. Electron Devices, vol. ED-16, pp. 64–77; 1969.
    • (1969) IEEE Trans. Electron Devices , vol.ED-16 , pp. 64-77
    • Scharfetter, D.L.1    Gummel, H.K.2
  • 18
    • 0022144793 scopus 로고
    • “Correlation between MOST 1/f noise and CCD transfer inefficiency,”
    • L. K. J. Vandamme and R. G. M. Penning De Vries, “Correlation between MOST 1/f noise and CCD transfer inefficiency,” Solid-state Electron., vol. 28, pp. 1049–1056, 1985.
    • (1985) Solid-state Electron. , vol.28 , pp. 1049-1056
    • Vandamme, L.K.J.1    Penning De Vries, R.G.M.2
  • 19
    • 84939024013 scopus 로고
    • “Analytical models of threshold voltages and breakdown voltage of short-channel MOSFET's derived from twodimensional analysis,”
    • T. Toyabe and S. Asai, “Analytical models of threshold voltages and breakdown voltage of short-channel MOSFET's derived from twodimensional analysis,” IEEE J. Solid-state Circuits, vol. SC-14, pp. 375–383, 1979.
    • (1979) IEEE J. Solid-state Circuits , vol.SC-14 , pp. 375-383
    • Toyabe, T.1    Asai, S.2
  • 20
    • 0022891057 scopus 로고
    • “Characterization and modeling of mismatch in MOS transistors for precision analog design,”
    • K. R. Lakshmikumar et al., “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-state Circuits, vol. SC-21, pp. 1057–1066, 1986.
    • (1986) IEEE J. Solid-state Circuits , vol.SC-21 , pp. 1057-1066
    • Lakshmikumar, K.R.1
  • 22
    • 0018027059 scopus 로고
    • “A charge-oriented model for MOS transistor capacitors,”
    • D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitors,” IEEE J. Solid-state Circuits, vol. SC-13, pp. 703–708, 1978.
    • (1978) IEEE J. Solid-state Circuits , vol.SC-13 , pp. 703-708
    • Ward, D.E.1    Dutton, R.W.2
  • 23
    • 0020125545 scopus 로고
    • “A comparison of semiconductor devices for high-speed logic,”
    • P. M. Solomon, “A comparison of semiconductor devices for high-speed logic,” Proc. IEEE, vol. 70, pp. 489–509, 1982.
    • (1982) Proc. IEEE , vol.70 , pp. 489-509
    • Solomon, P.M.1
  • 26
    • 0022751541 scopus 로고
    • “A fine emitter transistor fabricated by electronbeam lithography for high-speed bipolar LSI's,”
    • Y. Tamaki et al., “A fine emitter transistor fabricated by electronbeam lithography for high-speed bipolar LSI's,” IEEE Electron Device Lett., vol. EDL-7, pp. 425–427, 1986.
    • (1986) IEEE Electron Device Lett. , vol.EDL-7 , pp. 425-427
    • Tamaki, Y.1
  • 28
    • 0023559726 scopus 로고
    • “Perspective to BiCMOS VLSIs,”
    • May
    • M. Kubo, “Perspective to BiCMOS VLSIs,” in Proc. Symp. VLSI Circuits, May 1987, pp. 89–90.
    • (1987) Proc. Symp. VLSI Circuits , pp. 89-90
    • Kubo, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.