500MHz 32b 0.4μm CMOS RISC processor LSI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1994, Pages 214-215

  Suzuki, Kazumasa ^a   Yamashina, Masakazu ^a   Nakayama, Takashi ^a   Izumikawa, Masanori ^a   Nomura, Masahiro ^a   Igura, Hiroyuki ^a   Heiuchi, Hideki ^a   Goto, Junichi ^a   Inoue, Toshiaki ^a   Koseki, Youichi ^a   Abiko, Hitoshi ^a   Okabe, Kazuhiro ^a   Ono, Atsuki ^a   Yano, Youichi ^a   Yamada, Hachiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SCHEMATIC DIAGRAMS;

CLOCK DISTRIBUTION SCHEME; DOUBLE STAGE PIPELINE ADDER; RISC PROCESSORS;

LSI CIRCUITS;

EID: 0028087538     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)