1 Gb DRAM for file applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 38, Issue , 1995, Pages

  Sugibayashi, Tadahiko ^a   Naritake, Isao ^a   Utsugi, Satoshi ^a   Shibahara, Kentaro ^a   Oikawa, Ryuichi ^a   Mori, Hidemitsu ^a   Iwao, Shouichi ^a   Murotani, Tatsunori ^a   Koyama, Kuniaki ^a   Fukuzawa, Shinichi ^a   Itani, Toshiro ^a   Kasama, Kunihiko ^a   Okuda, Takashi ^a   Ohya, Shuichi ^a   Ogawa, Masaki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATABASE SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; MONTE CARLO METHODS;

DIAGONAL BIT LINE; FLEXIBLE MULTIMACRO ARCHITECTURE; TIME SHARED OFFSET CANCEL SENSING SCHEME;

RANDOM ACCESS STORAGE;

EID: 0029255749     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)