2.5 V delay-locked loop for an 18Mb 500MB/s DRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1994, Pages 300-301

  Lee, Thomas H ^a   Donnelly, Kevin ^a   Ho, John ^a   Zerbe, Jared ^a   Johnson, Mark ^a   Ishikawa, Toru ^a  

^a RAMBUS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN; INTEGRATED CIRCUITS; PERFORMANCE; PHASE SHIFTERS; SCHEMATIC DIAGRAMS;

DELAY LOCKED LOOP; DRAMS; DUTY CYCLE CORRECTION; UNLIMITED PHASE SHIFT;

RANDOM ACCESS STORAGE;

EID: 0028076601     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)