A 3.8-ns CMOS 16 X 16-b Multiplier Using Complementary Pass-Transistor Logic

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 2, 1990, Pages 388-395

  Yano, Kazuo ^a   Shimizu, Akihiro ^a   Nishida, Takashi ^a   Saito, Masayoshi ^a   Shimohigashi, Katsuhiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, FREQUENCY MULTIPLYING; INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICES, MOS;

CMOS MULTIPLIER; CMOS OUTPUT INVERTERS; COMPLEMENTARY PASS-TRANSISTOR LOGIC;

LOGIC CIRCUITS;

EID: 0025419522     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.52161     Document Type: Article

References (11)

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