A 15-ns 16-Mb CMOS SRAM with Interdigitated Bit-Line Architecture

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 11, 1992, Pages 1497-1503

  Matsumiya, Masato ^a   Kawashima, Shoichiro ^a   Sakata, Makoto ^a   Ookura, Masahiko ^a   Miyabo, Torn ^a   Koga, Torn ^a   Itabashi, Kazuo ^a   Mizutani, Kazuhiro ^a   Shimada, Hiroshi ^a   Suzuki, Noriyuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; SEMICONDUCTOR STORAGE; THIN FILM DEVICES;

CMOS SRAM; CURRENT SENSE AMPLIFIER; DOUBLE-GATE PMOS TFT; HIERARCHICAL SENSE AMPLIFIER; INTERDIGITATED BIT-LINE ARCHITECTURE; LOCAL SENSE AMPLIFIER; SOFT-ERROR IMMUNITY;

RANDOM ACCESS STORAGE;

EID: 0026954381     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.165328     Document Type: Article

References (11)

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