A 7-ns 140-mW 1-Mb CMOS SRAM with Current Sense Amplifier

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 11, 1992, Pages 1511-1518

  Sasaki, Katsuro ^a   Ishibashi, Koichiro ^a   Ueda, Kiyotsugu ^a   Komiyaji, Kunihiro ^a   Yamanaka, Toshiaki ^a   Hashimoto, Naotaka ^a   Toyoshima, Hiroshi ^a   Kojima, Fumio ^a   Shimizu, Akihiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; PHOTOLITHOGRAPHY; SEMICONDUCTOR STORAGE;

CMOS SRAM; CURRENT SENSE AMPLIFIER; PARALLEL TRANSISTOR LAYOUT; PHASE-SHIFTING PHOTOLITHOGRAPHY; PRE-OUTPUT BUFFER; VOLTAGE-SENSE AMPLIFIER;

RANDOM ACCESS STORAGE;

EID: 0026953436     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.165330     Document Type: Article

References (5)

1. K. Sasaki et al., “A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier,” in ISSCC Dig. Tech. Papers, Feb. 1992, p. 208.
2. E. Seevinck, “A current sense-amplifier for fast CMOS SRAMs,” in Symp. VLSI Circuits Dig. Tech. Papers, May 1990, p. 71.
3. O. Minato et al., “A HI-CMOSII 8K x 8 b static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, p. 256.
4. T. Yamanaka et al., “A 5.9 μm’ super low power SRAM cell using a new phase-shift lithography,” in IEDM Tech. Dig., Dec. 1990, p. 477.
5. J. S. Browning et al., “Single event upset rate estimates for a 16-K CMOS RAM,” IEEE Trans. Nucl. Sci., vol. NS-32, no. 6, pp. 4133-4139, Dec. 1985.