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Volumn , Issue , 1994, Pages 119-120
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Source sensed SRAM (S3) cell
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Author keywords
[No Author keywords available]
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Indexed keywords
ELECTRIC DELAY LINES;
ELECTRIC NETWORK ANALYSIS;
ELECTRIC NETWORK TOPOLOGY;
LOGIC DESIGN;
LOGIC GATES;
MULTIPLEXING;
RANDOM ACCESS STORAGE;
RESPONSE TIME (COMPUTER SYSTEMS);
CELL GROUND BUS;
DATA ACCESS DELAYS;
INTERCONNECT DENSITY;
INTERSIGNAL CROSS COUPLING;
STATIC RANDOM ACCESS MEMORIES;
CELLULAR ARRAYS;
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EID: 0028594576
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (1)
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References (8)
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