A 9-ns 16-Mb CMOS SRAM with Offset-Compensated Current Sense Amplifier

IEEE Journal of Solid-State Circuits

Volumn 28, Issue 11, 1993, Pages 1119-1124

  Seno, Katsunori ^a   Knorpp, Kurt ^b   Shu, Lee Lean ^b   Teshima, Naoki ^a   Kihara, Hiroki ^a   Sato, Hiroshi ^a   Miyaji, Fumio ^a   Takeda, Minoru ^a   Sasaki, Masayoshi ^a   Tomo, Yoichi ^b   Chuang, Patrick T ^b   Kobayashi, Kazuyoshi ^a  

^a Sony Corporation Semiconductor Network Company   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; VOLTAGE CONTROL;

OFFSET COMPENSATION EFFECT; STABILIZED FEEDBACK CURRENT SENSE AMPLIFIER; STATIC RANDOM ACCESS STORAGE; TEST CIRCUIT;

RANDOM ACCESS STORAGE;

EID: 0027702073     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.245591     Document Type: Article

References (7)

1. S. Flannagan et al., “8ns CMOS 64k × 4 and 256k × l SRAMs,” ISSCC Dig. Tech. Papers, Feb. 1990, pp. 134–135.
2. K. Sasaki et al., “A 7ns 140mW 1Mb CMOS SRAM with current sense amplifier,” ISSCC Dig. Tech. Papers, Feb. 1992, pp. 208–209.
3. E. Seevinck et al., “Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM’s,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525–535, Apr. 1991.
4. G. C. Temes and W. H. Ki, “Fast CMOS current amplifier and buffer stage,” Electron. Lett., vol. 23, no. 13, pp. 696–697, June 1987.
5. K. Arimoto et al, “A 60ns 3.3V 16M DRAM,” ISSCC Dig. Tech. Papers, 1989, pp. 244–245.
6. S. Mori et al., “A 45ns 16Mb DRAM with a merged match-line test architecture,” ISSCC Dig. Tech. Papers, 1991, 110–111.
7. Y. Tomo et al., “0.35μm rule device pattern fabrication using high absorption-type novolac photoresist in single layer deep ultraviolet lithography,” J. Vac. Sci. Technol. B, vol. 10, no. 6, pp. 2576–2580, Nov./Dec. 1992.