A 3.3-V 12-ns 16-Mb CMOS SRAM

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 11, 1992, Pages 1490-1496

  Goto, Hiroyuki ^a   Ohkubo, Hiroaki ^a   Kondou, Kenji ^a   Ohkawa, Masayoshi ^a   Mitani, Hitoshi ^a   Horiba, Shinichi ^a   Soeda, Masakazu ^a   Hayashi, Fumihiko ^a   Hachiya, Yutaro ^a   Shimizu, Toshiyuki ^a   Ando, Manabu ^a   Matsuda, Zensuke ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; OPTIMIZATION; REDUNDANCY; SEMICONDUCTOR STORAGE;

AUTOMATED TRANSISTOR SIZE OPTIMIZER; CMOS SRAM; DELAY MODEL FITTING; READ-BUS MIDLEVEL PRESET SCHEME; READ-BUS TRANSMISSION DELAY;

RANDOM ACCESS STORAGE;

EID: 0026953170     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.165327     Document Type: Article

References (10)

1. F. Miyaji et al., “A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads,” IEEE J. Solid-State Circuits, vol. 24, pp. 1213-1218, Oct. 1989.
2. S. Aizaki et al., “A 15-ns 4-Mbit CMOS SRAM,” IEEE J. Solid-State Circuits, vol. 25, pp. 1063-1067, Oct. 1990.
3. T. Hirose et al., “A 20-ns 4-Mbit CMOS SRAM with hierarchical word decoding architecture,” IEEE J. Solid-State Circuits, vol. 25, pp. 1068-1074, Oct. 1990.
4. K. Sasaki et al., “A 23-ns 4-Mbit CMOS SRAM with 0.2-μA standby current,” IEEE J. Solid-State Circuits, vol. 25, pp. 1075-1081, Oct. 1990.
5. T. Ootani et al., “A 4-Mbit CMOS SRAM with a PMOS thin-film-transistor load cell,” IEEE J. Solid-State Circuits, vol. 25, pp. 1082-1092, Oct. 1990.
6. S. Murakami et al., “A 21-mW 4-Mb CMOS SRAM for battery operation,” IEEE J. Solid-State Circuits, vol. 26, pp. 1563-1570, Nov. 1991.
7. K. Nakamura et al., “A 6 ns 4 Mb ECL I/O BiCMOS SRAM with LV-TTL mask option,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 212-213.
8. H. Kato et al., “A 9 ns 4 Mb BiCMOS SRAM with 3.3 V operation,” in ISSCC Dig. Tech. Papers, Feb. 1992, pp. 210-211.
9. H. Sinohara et al., “A 4.5 ns 256K CMOS SRAM with tri-level word line,” in ISSCC Dig. Tech. Papers, Feb. 1985, pp. 62-63.
10. H. Ohkubo et al., “16 Mbit SRAM cell technologies for 2.0 V operation,” in IEDM Tech. Dig., 1991, pp. 481-484.