A Battery Backup 64K CMOS RAM with Double-Level Aluminum Technology

IEEE Journal of Solid-State Circuits

Volumn 18, Issue 5, 1983, Pages 494-498

  Watanabe, Takayuki ^a   Hayasi, Mineo ^a   Sasaki, Isao ^a   Akatsuka, Yasuo ^a   Tsujide, Tohru ^a   Yamamoto, Hirohiko ^a   Kudoh, Osamu ^a   Takahashi, Sakari ^a   Hara, Toshio ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS RAM;

DATA STORAGE, DIGITAL;

EID: 0020833208     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1983.1051983     Document Type: Article

References (4)

1. K. Ochii et al., “A 15mW standby power 64K CMOS RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 260-261.
2. S. Konishi et al., “A 64 kbit CMOS RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 258-259.
3. O. Minato et al., “A Hi-CMOS 8K × 8 bit static RAM,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 256-257.
4. Y. Akatsuka et al., “Fully static CMOS 16K RAM using dynamic circuitry technique,” in 6th Europ. Solid State Circuit Conf. Dig. Tech. Papers, Sept. 1980, pp. 155-157.