Characterization of leakage power in CMOS technologies

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 1998, Pages 185-188

  Ferré, Antoni ^a   Figueras, Joan ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CORRELATION METHODS; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; LEAKAGE CURRENTS; MATHEMATICAL MODELS;

CELL LEVELS; CMOS DIGITAL CIRCUITS; CMOS TECHNOLOGY; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; NOMINAL VALUES; STANDARD CELL; SUB-THRESHOLD LEAKAGE;

LEAKAGE CURRENTS; CMOS INTEGRATED CIRCUITS;

LEAKAGE POWER;

EID: 0032276918     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.1998.814859     Document Type: Conference Paper

References (11)

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