Germanium Nanodevices and Technology

Springer Series in Advanced Microelectronics

Volumn 27, Issue , 2007, Pages 293-313

  Chui, C O ^a   Saraswat, K C ^a  

^a Stanford University   (United States)

Author keywords

Atomic Layer Deposition; Gate Leakage; Gate Length; Rapid Thermal Processing; Thread Dislocation Density

Indexed keywords

EID: 85103570064     PISSN: 14370387     EISSN: 21976643     Source Type: Book Series    
DOI: 10.1007/978-3-540-71491-0_13     Document Type: Chapter

References (27)

1. The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2004 Update. (http://public.itrs.net/)
2. E.J. Nowak, “Maintaining the benefits of CMOS scaling when scaling bogs down,” IBM J. Res. & Dev., vol. 46, pp. 169–180, 2002
3. M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., vol. 18, pp. 361–363, 1997
4. M. Lundstrom and Z. Ren, “Essential physics of carrier transport in nanoscale MOSFETs,” IEEE Trans. Electron Dev., vol. 49, pp. 133–141, 2002
5. A. Lochtefeld and D.A. Antoniadis, “On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?” IEEE Electron Dev. Lett., vol. 22, pp. 95–97, 2001
6. S. Takagi, “Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport,” VLSI Symp. Tech. Dig., pp. 115–116, 2003
7. Electronic Archive of New Semiconductor Materials, Characteristics and Properties, Ioffe Physico-Technical Institute. (http://www.ioffe.rssi.ru/SVA/NSM/Semicond/)
8. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majum-dar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and lower-power logic transistor applications,” IEEE Trans. Nanotech., vol. 4, pp. 153–158, 2005
9. C.O. Chui, A.K. Okyay, and K.C. Saraswat, “Effective dark current suppression with asymmetric MSM photodetectors in Group IV semiconductors,” IEEE Photon. Technol. Lett., vol. 15, pp. 1585–1587, 2003
10. C.O. Chui, H. Kim, P.C. McIntyre, and K.C. Saraswat, “A germanium NMOS-FET process integrating metal gate and improved hi-k dielectrics,” IEEE IEDM Tech. Digest, pp. 437–440, 2003
11. 1−x on silicon by molecular beam epitaxy,” Appl. Phys. Lett., vol. 44, pp. 102–104, 1984
12. D.J. Eaglesham and M. Cerullo, “Low-temperature growth of Ge on Si(100),” Appl. Phys. Lett., vol. 58, pp. 2276–2278, 1991
13. M.T. Currie, S.B. Samavedam, T.A. Langdo, C.W. Leitz, and E.A. Fitzgerald, “Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing,” Appl. Phys. Lett., vol. 72, pp. 1718–1720, 1998
14. Hsin-Chiao Luan, D.R. Lim, K.K. Lee, K.M. Chen, J.G. Sandland, K. Wada, and L.C. Kimerling, “High-quality Ge epilayers on Si with low threading-dislocation densities,” Appl. Phys. Lett., vol. 75, pp. 2909–2911, 1999
15. A. Nayfeh, C.O. Chui, K.C. Saraswat, and T. Yonehara, “Effects of hydrogen annealing on heteroepitaxial-Ge layers on Si: Surface roughness and electrical quality,” Appl. Phys. Lett., vol. 85, pp. 2815–2817, 2004
16. A. Nayfeh, C.O. Chui, T. Yonehara, and K.C. Saraswat, “Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si,” IEEE Electron Device Lett., vol. 26, pp. 311–313, 2005
17. N. Sato and T. Yonehara, “Hydrogen annealed silicon-on-insulator,” Appl. Phys. Lett., vol. 65, pp. 1924–1926, 1994
18. D.J. Hymes and J.J. Rosenberg, “Growth and materials characterization of native germanium oxynitride thin films on germanium,” J. Electrochem. Soc., vol. 135, pp. 961–965, 1988
19. C.O. Chui, F. Ito, and K.C. Saraswat, “Scalability and electrical properties of germanium oxynitride MOS dielectrics,” IEEE Electron Dev. Lett., vol. 25, pp. 613–615, 2004
20. C.O. Chui, D.-I. Lee, A.A. Singh, P.A. Pianetta, and K. C. Saraswat, “Zirconia-germanium interface photo-emission spectroscopy using synchrotron radiation,” J. Appl. Phys., vol. 97, p. 113518, 2005
21. C.O. Chui, H. Kim, P.C. McIntyre, and K.C. Saraswat, “Atomic layer deposition of high-k dielectric for germanium MOS applications: substrate surface preparation,” IEEE Electron Dev. Lett., vol. 25, 2004
22. C.O. Chui, S. Ramanathan, B.B. Triplett, P.C. McIntyre, and K. C. Saraswat, “Germanium MOS capacitors incorporating ultrathin high-k gate dielectric,” IEEE Electron Dev. Lett., vol. 23, pp. 473–475, 2002
23. C.O. Chui, K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, and K.C. Saraswat, “Activation and diffusion studies of ion-implanted p-and n-dopants in germa-nium,” Appl. Phys. Lett., vol. 83, 2003
24. W.C. Dunlap, Jr., “Diffusion of impurities in germanium,” Phys. Rev., vol. 94, pp. 1531–1540, 1954
25. ◦ C germanium MOSFET technology with high-k dielectric and metal gate,” IEEE IEDM Tech. Digest, pp. 437–440, 2002
26. 3 gate dielectrics,” VLSI Symp. Tech. Dig., pp. 119–120, 2003
27. 2 gate dielectrics and TaN gate electrode,” IEEE IEDM Tech. Digest, pp. 433–436, 2003