Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

Proceedings - Real-Time Systems Symposium

Volumn 2018-December, Issue , 2019, Pages 230-241

  Agrawal, Ankit ^a   Mancuso, Renato ^b   Pellizzoni, Rodolfo ^c   Fohler, Gerhard ^a  

^a University of Koblenz Landau   (Germany)

^b BOSTON UNIVERSITY   (United States)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Dynamic Memory Bandwidth Regulation; Memory Scheduling; Multicore Processing; Real time Systems; WCET in Multicore

Indexed keywords

BANDWIDTH; CACHE MEMORY; DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING;

DYNAMIC MEMORY; INTEGRATED MODULAR AVIONICS; MEMORY SCHEDULING; MULTI CORE; MULTI-CORE EMBEDDED SYSTEMS; MULTI-CORE PROCESSING; RESPONSE TIME COMPUTATION; WORST CASE RESPONSE TIME;

REAL TIME SYSTEMS;

EID: 85061547103     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2018.00040     Document Type: Conference Paper

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