Memory Servers for Multicore Systems

2016 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2016 - Proceedings

Volumn , Issue , 2016, Pages

  Pellizzoni, Rodolfo ^a   Yun, Heechul ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b UNIVERSITY OF KANSAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; INTERACTIVE COMPUTER SYSTEMS;

DELAY ANALYSIS; FIXED PRIORITY SCHEDULING; IMPROVING SYSTEMS; MEMORY SERVERS; MULTI-CORE SYSTEMS; PHYSICAL RESOURCES; SCHEDULABILITY CONDITIONS; SERVER INTERFACES;

REAL TIME SYSTEMS;

EID: 84971273102     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2016.7461339     Document Type: Conference Paper

References (40)

1. B. Akesson, K. Goossens, and M. Ringhofer. Predator: a predictable SDRAM memory controller. In Hardware/software codesign and system synthesis (CODES+ISSS). ACM, 2007.
2. A. Bastoni, B. B. Brandenburg, and J. H. Anderson. Cache-related preemption and migration delays: Empirical approximation and impact on schedulability. In OSPERT, 2010.
3. F. Bellosa. Process cruise control: Throttling memory access in a soft real-time environment. In Symposium on Operating Systems Principles (SOSP, Poster Session), 1997.
4. E. Bini and G. Buttazzo. Schedulability analysis of periodic fixed priority systems. IEEE Transactions on Computers, 53(11):1462-1473, 2004.
5. Certification Authorities Software Team (CAST). CAST-32 Position Paper: Multi-core Processors.
6. N. Chatterjee, N. Muralimanohar, R. Balasubramonian, A. Davis, and N. Jouppi. Staged reads: Mitigating the impact of DRAM writes on DRAM reads. In HPCA, 2012.
7. L. Ecco, S. Tobuschat, S. Saidi, and R. Ernst. A mixed critical memory controller using bank privatization and fixed priority scheduling. In IEEE RTCSA, 2014.
8. Freescale. e500mc Core Reference Manual (Rev.3), 2013.
9. S. Goossens, B. Akesson, and K. Goossens. Conservative openpage policy for mixed tim-criticality memory controllers. In Design, Automation and Test in Europe (DATE), 2013.
10. A. Hansson, N. Agarwal, A. Kolli, T. Wenisch, and A. Udipi. Simulating DRAM controllers for future system architecture exploration. In International Symposium on Performance Analysis of Systems and Software (ISPASS), 2014.
11. D. Hardy and I. Puaut. Estimation of cache related migration delays for multi-core processors with shared instruction caches. In RTNS, 2009.
12. R. Inam, M. Behnam, T. Nolte, and M. Sjodin. Compositional analysis for the multi-resource server. In ETFA, 2015.
13. R. Inam, N. Mahmud, M. Behnam, T. Nolte, and M. Sjodin. The multiresource server for predictable execution on multi-core platforms. In RTAS, pages 1-12. IEEE, 2014.
14. Intel. Intel-R 64 and IA-32 Architectures Software Developer Manuals, 2012.
15. A. Jaleel. Memory characterization of workloads using instrumentationdriven simulation: a pin-based memory characterization of the SPEC CPU2000 and SPEC CPU2006 benchmark suites. Intel Corporation, VSSAD, 2007.
16. H. Kim, D. de Niz, B. Andersson, M. Klein, O. Mutlu, and R. R. Rajkumar. Bounding Memory Interference Delay in COTS-based Multi- Core Systems. In RTAS, 2014.
17. Y. Krishnapillai, Z. P. Wu, and R. Pellizzoni. A Rank-Switching, Open- Row DRAM Controller for Time-Predictable Systems. In Euromicro Conference on Real-Time Systems (ECRTS), pages 27-38. IEEE, 2014.
18. R. Mancuso, R. Pellizzoni, M. Caccamo, L. Sha, and H. Yun. Response- Time Analysis for Single Core Equivalence Framework. In Euromicro Conference on Real-Time Systems (ECRTS), 2015.
19. C. Natarajan, B. Christenson, and F. Briggs. A study of performance impact of memory controller features in multi-processor server environment. In Proceedings of the 3rd workshop on Memory performance issues, pages 80-87. ACM, 2004.
20. J. Nowotsch and M. Paulitsch. Leveraging multi-core computing architectures in avionics. In EDCC, pages 132-143. IEEE, 2012.
21. J. Nowotsch, M. Paulitsch, D. Buhler, H. Theiling, S. Wegener, and M. Schmidt. Multi-core interference-sensitive wcet analysis leveraging runtime resource capacity enforcement. In Euromicro Conference on Real-Time Systems (ECRTS), pages 109-118. IEEE, 2014.
22. M. Paolieri, E. Quiñones, and F. J. Cazorla. Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions. ACM TECS, 12(1s):64, 2013.
23. R. Pellizzoni and H. Yun. Memory Server Code Repository. Available at https://ece.uwaterloo.ca/-rpellizz/techreps/servercode.zip.
24. P. Radojković, S. Girbal, A. Grasset, E. Quiñones, S. Yehia, and F. J. Cazorla. On the evaluation of the impact of shared resources in multithreaded cots processors in time-critical environments. ACM TACO, 8(4):34, 2012.
25. J. Reineke, I. Liu, H. Patel, S. Kim, and E. Lee. PRET DRAM controller: Bank privatization for predictability and temporal isolation. In CODES+ISSS. ACM, 2011.
26. S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. Owens. Memory access scheduling. In ACM SIGARCH Computer Architecture News. ACM, 2000.
27. S. Schliecker and R. Ernst. Real-time Performance Analysis of Multiprocessor Systems with Shared Memory. ACM Trans. Embed. Comput. Syst., 10(2):22:1-22:27, Jan. 2011.
28. A. Schranzhofer, J. Chen, and L. Thiele. Timing analysis for TDMA arbitration in resource sharing systems. In Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 2010.
29. A. Schranzhofer, R. Pellizzoni, J. Chen, L. Thiele, and M. Caccamo. Timing analysis for resource access interference on adaptive resource arbiters. In RTAS. IEEE, 2011.
30. L. Sha, M. Caccamo, R. Mancuso, J.-E. Kim, M.-K. Yoon, R. Pellizzoni, H. Yun, R. Kegley, D. P. Greg, Arundale, and R. Bradford. Single Core Equivalent Virtual Machines for hard real-time computing on multicore processors. Technical report, University of Illinois, 2014.
31. Z. Shi and A. Burns. Real-time communication analysis for on-chip networks with wormhole switching. In IEEE International Symposium on Networks-on-Chip, pages 161-170, 2008.
32. I. Shin and I. Lee. Periodic resource model for compositional real-time guarantees. In Real-Time Systems Symposium (RTSS). IEEE, 2003.
33. P. Valsan, H. Yun, and F. Farshchi. Taming non-blocking caches to improve isolation in multicore real-time systems. In RTAS, 2016.
34. Z. Wu, Y. Krish, and R. Pellizzoni. Worst Case Analysis of DRAM Latency in Multi-Requestor Systems. In RTSS, 2013.
35. A. Wulf and A. McKee. Hitting the memory wall: implications of the obvious. ACM SIGARCH computer architecture news, 23(1):20-24, 1995.
36. G. Yao, H. Yun, Z. Wu, R. Pellizzoni, M. Caccamo, and L. Sha. Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems. IEEE Transactions on Computers, 2015.
37. H. Yun, R. Mancuso, Z. Wu, and R. Pellizzoni. PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platforms. In RTAS, 2014.
38. H. Yun, R. Pellizzoni, and P. K. Valsan. Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems. In Euromicro Conference on Real-Time Systems (ECRTS), 2015.
39. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. Memory Access Control in Multiprocessor for Real-time Systems with Mixed Criticality. In Euromicro Conference on Real-Time Systems (ECRTS), 2012.
40. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multi-core Platforms. In RTAS, 2013.