Schedulability analysis for memory bandwidth regulated multicore real-time systems

IEEE Transactions on Computers

Volumn 65, Issue 2, 2016, Pages 601-614

  Yao, Gang ^a   Yun, Heechul ^b   Wu, Zheng Pei ^c   Pellizzoni, Rodolfo ^c   Caccamo, Marco ^a   Sha, Lui ^a  

^a University of Illinois at Urbana Champaign   (United States)

^b University of Kansas   (United States)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Gem5; Memory access control; Real time system; Schedulability analysis; Scheduling

Indexed keywords

ACCESS CONTROL; BANDWIDTH; COMPUTER ARCHITECTURE; INTERACTIVE COMPUTER SYSTEMS; MEMORY ARCHITECTURE; SCHEDULING; SOFTWARE ARCHITECTURE;

GEM5; MEMORY ACCESS; MULTICORE ARCHITECTURES; PROPOSED ARCHITECTURES; REAL TIME PERFORMANCE; SCHEDULABILITY ANALYSIS; SYSTEM ARCHITECTURES; WORST CASE RESPONSE TIME;

REAL TIME SYSTEMS;

EID: 84962052761     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2015.2425874     Document Type: Article

References (32)

1. Aeronautical Radio Inc. ARINC 653 Specification [Online]. Available: http://www.arinc.com/, June 2013
2. B. Akesson, K. Goossens, and M. Ringhofer. "Predator: A predictable SDRAM memory controller". in Proc. 5th IEEE/ACM Int. Conf. Hardware/Softw. Codesign Syst. Synthesis, 2007, pp. 251-256
3. B. Akesson, L. Steffens, E. Strooisma, and K. Goossens. "Real-time scheduling using credit-controlled static-priority arbitration". in Proc. 14th IEEE Int. Conf. Embedded Real-Time Comput. Syst. Appl., 2008, pp. 3-14
4. M. Alvarez, E. Salami, A. Ramirez, and M. Valero. "A performance characterization of high definition digital video decoding using H.264/AVC". in Proc. IEEE Int. Workload Characterization Symp., Oct. 2005, pp. 24-33
5. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. "The gem5 simulator". SIGARCH Comput. Archit. News, vol. 39, no. 2, pp. 1-7, 2011
6. A. Burns, and S.K. Baruah. "Sustainability in real-time scheduling". J. Comput. Sci. Eng., vol. 2, no. 1, pp. 74-97, 2008
7. R.I. Davis, and A. Burns. "Resource sharing in hierarchical fixed priority pre-emptive systems". in Proc. 27th IEEE Int. Real-Time Systems Symp., Dec. 2006, pp. 257-270
8. E. Ebrahimi, C.J. Lee, O. Mutlu, and Y.N. Patt. "Fairness via source throttling: a configurable, and high-performance fairness substrate for multi-core memory systems". ACM SIGPLAN Notices, vol. 45, no. 3, pp. 335-346, 2010
9. S. A. Edwards, and E. A. Lee. "The case for the precision timed (PRET) machine". in Proc. 44th Annu. Des. Autom. Conf., 2007
10. Freescale. P4080 website [Online]. Available: http://www. freescale.com, Feb. 2014
11. Intel. Intel 64, and IA-32 Architectures Optimization Reference Manual [Online]. Available: http://download.intel.com/products/processor/manual/325383.pdf, June 2015
12. A. Kurdila, M. Nechyba, R. Prazenica, W. Dahmen, P. Binev, R. DeVore, and R. Sharpley. "Vision-based control of micro-airvehicles: Progress, and problems in estimation". in Proc. 43rd IEEE Conf. Decision Control, 2004, vol. 2, pp. 1635-1642
13. N. C. Audsley, A. Burns, M. Richardson, K. Tindell, and A. Wellings. "Applying new scheduling theory to static priority preemptive scheduling". Softw. Eng. J., vol. 8, no. 5, pp. 284-292, 1993
14. K. J. Nesbit, N. Aggarwal, J. Laudon, and J. E. Smith. "Fair queuing memory systems". in Proc. Int. Symp. Microarchit., 2006, pp. 208-222
15. M. Paolieri, E. Quiñones, F. J. Cazorla, G. Bernat, and M. Valero. "Hardware support for WCET analysis of hard real-time multicore systems". ACM SIGARCH Comput. Archit. News, vol. 37, pp. 57-68, 2009
16. R. Pellizzoni, E. Betti, S. Bak, G. Yao, J. Criswell, M. Caccamo, and R. Kegley. "A predictable execution model for COTS-based embedded systems". in Proc. Real-Time Embedded Technol. Appl. Symp., 2011, pp. 269-279
17. R. Pellizzoni, and M. Caccamo. "Toward the predictable integration of real-time COTS based systems". in Proc. Real-Time Syst. Symp., 2007, pp. 73-82
18. R. Pellizzoni, A. Schranzhofery, J. J. Cheny, M. Caccamo, and L. Thiele. "Worst case delay analysis for memory interference in multicore systems". in Proc. Des., Autom. Test Eur. Conf. Exhib., 2010, pp. 741-746
19. R. Rajkumar, K. Juvva, A. Molano, and S. Oikawa. "Resource kernels: A resource-centric approach to real-time, and multimedia systems". in Proc. SPIE/ACM Conf. Multimedia Comput. Netw., Jan. 1998, pp. 150-164
20. J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee. "PRET DRAM controller: Bank privatization for predictability, and temporal isolation". in Proc. 7th IEEE/ACM/IFIP Int. Conf. Hardware/Softw. Codesign Syst. Synthesis, 2011, pp. 99-108
21. J. Rosen, A. Andrei, P. Eles, and Z. Peng. "Bus access optimization for predictable implementation of real-time applications on multiprocessor systems-on-chip". in Proc. 28th IEEE Int. Real-Time Syst. Symp., 2007, pp. 49-60
22. S. Schliecker, M. Negrean, and R. Ernst. "Response time analysis on multicore ECUs with shared resources". IEEE Trans. Ind. Informat., vol. 5, no. 4, pp. 402-413, Nov. 2009
23. S. Schliecker, M. Negrean, and R. Ernst. "Bounding the shared resource load for the performance analysis of multiprocessor systems". in Proc. Des. Autom. Test Eur. Conf. Exhib., 2010, pp. 759-764
24. A. Schranzhofer, J. J. Chen, and L. Thiele. "Timing analysis for TDMA arbitration in resource sharing systems". in Proc. IEEE 16th Real-Time Embedded Technol. Appl. Symp., 2010, pp. 215-224
25. A. Schranzhofer, R. Pellizzoni, J. J. Chen, L. Thiele, and M. Caccamo. "Timing analysis for resource access interference on adaptive resource arbiters". in Proc. IEEE 17th Real-Time Embedded Technol. Appl. Symp., 2011, pp. 213-222
26. I. Shin, and I. Lee. "Periodic resource model for compositional real-time guarantees". in Proc. Real-Time Syst. Symp., 2003, pp. 2-13
27. L. Thiele, S. Chakraborty, and M. Naedele. "Real-time calculus for scheduling hard real-time systems". in Proc. IEEE Int. Symp. Circuits Syst., 2000, vol. 4, pp. 101-104
28. R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister, and C. Ferdinand. "Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems". IEEE Trans. CAD Integr. Circuits Syst., vol. 28, no. 7, pp. 966-978, Jul. 2009
29. G. Yao, R. Pellizzoni, S. Bak, E. Betti, and M. Caccamo. "Memorycentric scheduling for multicore hard real-time systems". Real-Time Syst., vol. 48, no. 6, pp. 681-715, 2012
30. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. "Memory access control in multiprocessor for real-time systems with mixed criticality". in Proc. 24th Euromicro Conf. Real-Time Syst., 2012, pp. 299-308
31. H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha. "MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms". in Proc. IEEE 19th Real-Time Embedded Technol. Appl. Symp., 2013
32. X. Zhang, S. Dwarkadas, and K. Shen. "Towards practical page coloring-based multicore cache management". in Proc. 4th Eur. Conf. Comput. Syst., 2009, pp. 89-102