Real-Time Computing on Multicore Processors

Computer

Volumn 49, Issue 9, 2016, Pages 69-77

  Sha, Lui ^a   Caccamo, Marco ^a   Mancuso, Renato ^a   Kim, Jung Eun ^a   Yoon, Man Ki ^a   Pellizzoni, Rodolfo ^b   Yun, Heechul ^c   Kegley, Russell B ^d   Perlman, Dennis R ^d   Arundale, Greg ^e   Bradford, Richard ^e  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF WATERLOO   (Canada)

^c UNIVERSITY OF KANSAS   (United States)

^d LOCKHEED MARTIN   (United States)

^e ROCKWELL COLLINS   (United States)

Author keywords

avionics computing; memory access conflicts; multicore architecture; multicore chips; multicore processing; real time systems; single core equivalence

Indexed keywords

AVIONICS; INTERACTIVE COMPUTER SYSTEMS; MEMORY ARCHITECTURE; SOFTWARE ARCHITECTURE;

MEMORY ACCESS; MULTI-CORE PROCESSING; MULTICORE ARCHITECTURES; MULTICORE CHIPS; SINGLE-CORE EQUIVALENCE;

REAL TIME SYSTEMS;

EID: 84987624705     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2016.271     Document Type: Article

References (11)

1. Certification Authorities Software Team, "Position Paper CAST-32, Multicore Processors," rev. 0, 2014; www .faa.gov/aircraft/air-cert/design-approvals/air-software/cast/cast-papers/media/cast-32.pdf.
2. L. Sha et al., Single-Core Equivalent Virtual Machines for Hard Real-Time Computing on Multicore Processors, tech. report, CS Dept., Univ. of Illinois at Urbana?Champaign, 2014; www.ideals.illinois.edu/handle/2142/55672.
3. H. Yun et al., "PALLOC: DRAM Bank-Aware Memory Allocator for Performance Isolation on Multicore Platform," Proc. IEEE 19th Real-Time Technology and Applications Symp. (RTAS 14), 2014, pp. 155-166.
4. H. Yun et al., "MemGuard: Memory Bandwidth Reservation System for Efficient Performance Isolation in Multicore Platforms," Proc. IEEE 18th Real-Time Technology and Applications Symp. (RTAS 13), 2013, pp. 55-64.
5. R. Mancuso et al., "WCET(m) Estimation in Multicore Systems Using Single Core Equivalence," Proc. 27th Euromicro Conf. Real-Time Systems (ECRTS 15), 2015, pp. 174-183.
6. R. Mancuso et al., "Real-Time Cache Management Framework for Multicore Architectures," Proc. IEEE 18th Real-Time Technology and Applications Symp. (RTAS 13), 2013, pp. 45-54.
7. J.-E. Kim et al., "Integrated Modular Avionics (IMA) Partition Scheduling with Conflict-Free I/O for Multicore Avionics Systems," Proc. IEEE 38th Computer Software and Applications Conf. (COMPSAC 14), 2014, pp. 321-331.
8. L. Sha, "Real-Time Virtual Machines for Avionics Software Porting and Development," Real-Time and Embedded Computing Systems and Applications, LNCS 2968, J. Chen and S. Hong, eds., Springer, 2004, pp. 123-135.
9. H. Kim et al., "Bounding Memory Interference Delay in COTS-Based Multicore Systems," Proc. IEEE 19th Real-Time Technology and Applications Symp. (RTAS 14), 2014, pp. 145-154.
10. R. Wilhelm et al., "The Worst-Case Execution Time Problem-Overview of Methods and Survey of Tools," ACM Trans. Programming Languages and Systems, vol. 7, no. 3, 2008, article no. 36.
11. L. Sha et al., "Position Paper on Minimal Multicore Avionics Certification Guidance," 4 Jun. 2016; https://1drv .ms/b/s!AqCnfGZqrIHshuIGAczwiy EUa5ZjTQ.