Energy efficient co-adaptive instruction fetch and issue

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2003, Pages 147-156

  Buyuktosunoglu, Alper ^a   Karkhanis, Tejas ^b   Albonesi, David H ^a   Bose, Pradip ^c  

^a University of Rochester   (United States)

^b University of Wisconsin Madison   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; COMBINATORIAL MATHEMATICS; DYNAMIC PROGRAMMING; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; QUEUEING NETWORKS; REQUIREMENTS ENGINEERING;

DYNAMIC SUPERSCALAR PROCESSOR; FETCH GATING; FRONT END INSTRUCTION DELIVERY; QUEUE ADAPTATION;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0038346240     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/859618.859636     Document Type: Conference Paper

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