-
1
-
-
0344841297
-
Adaptative mode control: A static-power-efficient cache design
-
H. Zhou, M. Toburen, E. Rotenberg, T. Conte, "Adaptative Mode Control: A Static-Power-Efficient Cache Design" in PACT'01, Barcelona, Spain, September 2001.
-
PACT'01, Barcelona, Spain, September 2001
-
-
Zhou, H.1
Toburen, M.2
Rotenberg, E.3
Conte, T.4
-
2
-
-
0034856732
-
Cache decay: Exploiting generational behavior to reduce cache leakage power
-
S. Kaxiras, Z. Hu, M. Martonosi, "Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power" in ISCA'01, Göteborg, Sweden, June 2001.
-
ISCA'01, Göteborg, Sweden, June 2001
-
-
Kaxiras, S.1
Hu, Z.2
Martonosi, M.3
-
3
-
-
0033358971
-
Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
-
K. Ghose, M.B. Kamble, "Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-line Segmentation" in ISLPED'99, San Diego, California, August 1999.
-
ISLPED'99, San Diego, California, August 1999
-
-
Ghose, K.1
Kamble, M.B.2
-
4
-
-
0029192697
-
Cache design trade-offs for power and performance optimization: A case study
-
C.L. Su, A.M. Despain, "Cache Design Trade-offs for Power and Performance Optimization: A Case Study" in ISLPED'95, Dana Pt., California, April 1995.
-
ISLPED'95, Dana Pt., California, April 1995
-
-
Su, C.L.1
Despain, A.M.2
-
5
-
-
0033715405
-
A comparative study of power efficient SRAM designs
-
J. Hezavei, N. Vijaykrishnan, M.J. Irwin, "A Comparative Study of Power Efficient SRAM Designs" in GLSVLSI'00, Evanston, Illinois, March 2000.
-
GLSVLSI'00, Evanston, Illinois, March 2000
-
-
Hezavei, J.1
Vijaykrishnan, N.2
Irwin, M.J.3
-
6
-
-
0032023709
-
Variable supply-voltage scheme for low-power high-speed CMOS digital design
-
March
-
T. Kuroda et. al., "Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design" in IEEE Journal of Solid-State Circuits (JSSC) vol. 33, no. 3, March 1998.
-
(1998)
IEEE Journal of Solid-State Circuits (JSSC)
, vol.33
, Issue.3
-
-
Kuroda, T.1
-
8
-
-
0029288557
-
Trends in low-power RAM circuit technologies
-
April
-
K. Itoh, K. Sasaki, Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies" in Proc. of the IEEE vol. 83 no. 4, April 1995.
-
(1995)
Proc. of the IEEE
, vol.83
, Issue.4
-
-
Itoh, K.1
Sasaki, K.2
Nakagome, Y.3
-
9
-
-
0025415048
-
Alpha-power law MOSFET model and its applications to CMOS inventer delay and other formulas
-
April
-
T. Sakurai, A.R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inventer Delay and Other Formulas" in IEEE Journal of Solid-State Circuits (JSSC) vol. 25 no. 2, April 1990.
-
(1990)
IEEE Journal of Solid-State Circuits (JSSC)
, vol.25
, Issue.2
-
-
Sakurai, T.1
Newton, A.R.2
-
11
-
-
0034844456
-
Locality vs. criticality
-
S.T. Srinivasan, R.D. Ju, A.R. Lebeck, C. Wilkerson, "Locality vs. Criticality" in ISCA'01, Göteborg, Sweden, June 2001.
-
ISCA'01, Göteborg, Sweden, June 2001
-
-
Srinivasan, S.T.1
Ju, R.D.2
Lebeck, A.R.3
Wilkerson, C.4
-
12
-
-
0034844926
-
Focusing processor policies via critical-path prediction
-
B. Fields, S. Rubin, R. Bodík, "Focusing Processor Policies via Critical-Path Prediction" in ISCA'01, Göteborg, Sweden, June 2001.
-
ISCA'01, Göteborg, Sweden, June 2001
-
-
Fields, B.1
Rubin, S.2
Bodík, R.3
-
13
-
-
84908877398
-
Non-vital loads
-
R. Rakvic, B. Black, D. Limaye, J.P. Shen, "Non-vital Loads" in HPCA'02, Cambridge, Massachusetts, February 2002.
-
HPCA'02, Cambridge, Massachusetts, February 2002
-
-
Rakvic, R.1
Black, B.2
Limaye, D.3
Shen, J.P.4
-
14
-
-
0029511540
-
Critical path reduction for scalar programs
-
M. Schlansker, V. Kathail, "Critical Path Reduction for Scalar Programs" in MICRO'95, Ann Arbor, Michigan, November 1995.
-
MICRO'95, Ann Arbor, Michigan, November 1995
-
-
Schlansker, M.1
Kathail, V.2
-
15
-
-
0005320209
-
Architectural level power/performance optimization and dynamic power estimation
-
G. Cai, C.H. Lim, "Architectural Level Power/Performance Optimization and Dynamic Power Estimation" in Proceedings of Cool Chips Tutorial, in conj. with MICRO'99, Haifa, Israel, November 1999.
-
Proceedings of Cool Chips Tutorial, in Conj. with MICRO'99, Haifa, Israel, November 1999
-
-
Cai, G.1
Lim, C.H.2
-
16
-
-
0003465202
-
The simpleScalar tool set, version 2.0
-
Technical report #1324, Computer Sciences Department, University of Wisconsin-Madison, June
-
D. Burger, T. Austin, "The SimpleScalar Tool Set, Version 2.0" Technical report #1324, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
-
(1997)
-
-
Burger, D.1
Austin, T.2
-
17
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
D. Brooks, V. Tiwari, M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations" in ISCA'00, Vancouver, Canada, June 2000.
-
ISCA'00, Vancouver, Canada, June 2000
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
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