Conserving Network Processor Power Consumption by Exploiting Traffic Variability

ACM Transactions on Architecture and Code Optimization

Volumn 4, Issue 1, 2007, Pages 4-

  Luo, Yan ^a   Yu, Jia ^b   Bhuyan, Laxmi N ^b   Yang, Jun ^c  

^a University of Massachusetts   (United States)

^b University of California Riverside   (United States)

^c University of Pittsburgh   (United States)

Author keywords

clock gating; Design; Experimentation; low power; Measurement; Network processor; Performance; scheduling

Indexed keywords

EID: 85013775152     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1216544.1216547     Document Type: Article

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