Combining compiler and runtime IPC predictions to reduce energy in next generation architectures

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 240-254

  Chheda, Saurabh ^a   Unsal, Osman ^b   Koren, Israel ^c   Krishna, C Mani ^c   Moritz, Csaba Andras ^c  

^a BlueRISC Inc   (United States)

^b Intel Research Center Barcelona   (Spain)

^c University of Massachusetts Amherst   (United States)

Author keywords

Adaptive voltage scaling; Compiler architecture interaction; Fetch throttling; Instruction level parallelism; Low power design

Indexed keywords

COMPUTER AIDED INSTRUCTION; COMPUTER ARCHITECTURE; INFORMATION ANALYSIS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SPEED CONTROL; VOLTAGE CONTROL;

ADAPTIVE VOLTAGE SCALING; COMPILER ARCHITECTURE INTERACTIONS; FETCH THROTTLING; INSTRUCTION LEVEL PARALLELISM; LOW POWER DESIGN;

PROGRAM COMPILERS;

EID: 4143102641     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/977091.977125     Document Type: Conference Paper

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