Combining compiler and runtime IPC predictions to reduce energy in next generation architectures

2004 Computing Frontiers Conference

Volumn , Issue , 2004, Pages 240-254

  Chheda, Saurabh ^a   Unsal, Osman ^b   Koren, Israel ^c   Krishna, C Mani ^c   Moritz, Csaba Andras ^c  

^a BlueRISC Inc   (United States)

^b Intel Research Center Barcelona   (Spain)

^c University of Massachusetts   (United States)

Author keywords

Adaptive voltage scaling; Compiler architecture interaction; Fetch throttling; Instruction level parallelism; Low power design

Indexed keywords

COMPUTER AIDED INSTRUCTION; COMPUTER ARCHITECTURE; INFORMATION ANALYSIS; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SPEED CONTROL; VOLTAGE CONTROL;

ADAPTIVE VOLTAGE SCALING; COMPILER ARCHITECTURE INTERACTIONS; FETCH THROTTLING; INSTRUCTION LEVEL PARALLELISM; LOW POWER DESIGN;

PROGRAM COMPILERS;

EID: 4143102641     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/977091.977125     Document Type: Conference Paper

References (35)

1. The standard performance evaluation corporation. http://www.spec.org, Deemember 2000.
2. A. Aho, R. Rethi, and J. Ullman. Compilers: rinciples, techniques, and tools. Addison-Wesley.
3. W. Amme, P. Braun, F. Thomasset, and E. Zehendner. Data dependence analysis of assembly code. In International Journal on Parallel Programming 28, 5, 2000.
4. C. J. Anderson and et al. Physical design of a fourth-generation power ghz microprocessor. In Proceedings of the 2001 IEEE International Solid-State Circuits Conference (ISSCC'01), February 2001.
5. A. Azevedo and et al. Profile-based dynamic voltage scheduling using program checkpoints. In Work in submission at the European Design Automation and Test Conference (DATE'02). ACM Press, June 2000.
6. I. R. Bahar and S. Manne. Power and energy reduction via pipeline balancing. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA'01), June 2001.
7. A. Baniasadi and A. Moshovos. Instruction flow-based front-end throttling for power-aware high-performance processors. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'01), August 2001.
8. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA'00). ACM Press, June 2000.
9. D. Burger and T. D. Austin. The simplescalar tool set, version 2.0. In University of Wisconsin-Madison Computer-Sciences Department Technical Report #1342, June 1997.
10. A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D. Albonesi. An adaptive issue queue for reduced power at high performance. In Proceedings of the Workshop on Power-Aware Computer Systems, ASPLOS IX, November 2000.
11. J. Cantin and D. Hill. Cache performance for selected spec cpu2000 benchmarks. Computer Architecture News, Vol. 29, No. 4, September 2001.
12. A. Chandrakasan and R. W. Brodersen. Low-power digital cmos design. Kluwer Academic Publishers.
13. B. Childers, H. Tang, and R. Melhem. Adapting processor supply voltage to instruction-level parallelism. In Proceedings of the KoolChips Workshp, in conjunction with MICRO'00, December 2000.
14. D. Folegnani and A. Gonzalez, Energy-effective issue queue. In Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA'01), June 2001.
15. S. Ghiasi, J. Casmira, and D. Grunwald. Using ipc variation in workloads with externally specified rates to reduce power consumption. In Proceedings of the Workshop on Complexity-Effective Design, ISCA27, June 2000.
16. D. Henry, B. Kuszmaul, G. Loh, and R. Sami. Circuits for wide-window superscalar processors. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA'00), June 2000.
17. G. Hinton and et al. The microarchitecture of the pentium 4 processor. Intel Technology Journal Q1, 2001.
18. C.-H. Hsu and U. Kremer. Compiler-directed dynamic voltage scaling based on program regions. Technical Report, Department of Computer Science, Rutgers University (DCS-TR-461), November 2001.
19. A. M. D. Inc. Quantispeed achitecture. AMD White Paper, September 2001.
20. W. Kever and et al. A 200mhz rise microprocessor with 128kb on-chip caches. In Proceedings of the 1997 IEEE International Solid-State Circuits Conference (ISSCC'97), February 1997.
21. A. Kowalczyk and et al. First-generation majc dual processor. In Proceedings of the 2001 IEEE International Solid-State Circuits Conference (ISSCC'01), February 2001.
22. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual International Symposium on Microarchitecture (MICRO'97). ACM Press, December 1997.
23. J. Leenstra and et al. A 1.8 ghz instruction buffer. In Proceedings of the 2001 IEEE International Solid-State Circuits Conference (ISSCC'01), February 2001.
24. D. Liu and C. Svensson. Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid-State Circuits (IEEE JSSC), 1993.
25. S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: Speculation control for energy reduction. In Proceedings of the 25nd International Symposium on Microarchitecture (MICRO'98), June 1998.
26. D. Marculescu. Power efficient processors using multiple supply voltages. In Proceedings of the Workshop on Compilers and Operating Systems for Low Power, December 2000.
27. R. Maro, Y. Bai, and I. Bahar. Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors. In Workshop on Power-Aware Computer Systems PACS'00, In conjunction with ASPLOS IX.
28. D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. Stan. Power issues related to branch prediction. In Proceedings of the 8th International Symposium on High-Performance Computer Architecture (HPCA8), February 2002.
29. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In Proceedings of the 34th Annual International Symposium on Microarchitecture, December 2001.
30. D. Shin, J. Kim, and S. Lee. Low-energy intra-task voltage scheduling using static timing analysis. In Proceedings of the Design Automation Conference (DAC'01). ACM Press, June 2000.
31. G. Sohi and S. Vajapayem, Instruction issue logic for high-performance interruptable pipelined processors. In Proceedings of the 14th International Symposium on Computer Architecture (ISCA14), June 1987.
32. E. Tune, D. Liang, D. Tullsen, and B. Calder. Dynamic predictions of critical path instructions. In Proceedings of the 7th International Symposium on High Performance Computer Architecture (HPCA7), January 2001.
33. O. S. Unsal, I. Koren, C. M. Krishna, and C. A. Moritz. Cool-fetch: Compiler-enabled power-aware fetch throttling. IEEE Computer Architecture Letters, 2002.
34. F. Weber. Hammer: The architecture of amd's next-generation processors. Microprocessor Forum, October 2001.
35. V. Zyuban and P. Kogge. Inherently lower-power high-performance superscalar architectures. In IEEE Transactions on Computers Vol. 50 No. 3, March 2001.