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Volumn , Issue , 2004, Pages 240-254
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Combining compiler and runtime IPC predictions to reduce energy in next generation architectures
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Author keywords
Adaptive voltage scaling; Compiler architecture interaction; Fetch throttling; Instruction level parallelism; Low power design
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Indexed keywords
COMPUTER AIDED INSTRUCTION;
COMPUTER ARCHITECTURE;
INFORMATION ANALYSIS;
OPTIMIZATION;
PARALLEL PROCESSING SYSTEMS;
REAL TIME SYSTEMS;
SPEED CONTROL;
VOLTAGE CONTROL;
ADAPTIVE VOLTAGE SCALING;
COMPILER ARCHITECTURE INTERACTIONS;
FETCH THROTTLING;
INSTRUCTION LEVEL PARALLELISM;
LOW POWER DESIGN;
PROGRAM COMPILERS;
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EID: 4143102641
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/977091.977125 Document Type: Conference Paper |
Times cited : (5)
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References (35)
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