Dual threshold voltages and substrate bias: Keys to high performance, low power, 0.1 μm logic designs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 69-70

  Thompson, S ^a   Young, I ^a   Greason, J ^a   Bohr, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS;

THRESHOLD VOLTAGES;

LOGIC DESIGN;

EID: 0030647286     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)