Microarchitecture-level leakage reduction with data retention

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 11, 2005, Pages 1324-1328

  Liao, Weiping ^a   Basile, Joseph M ^b   He, Lei ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache memories; Circuit modeling; Computer architecture; Power

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA REDUCTION; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER GENERATION; GATING AND FEEDING; WORD PROCESSING;

ADAPTIVE CACHE DECAY; LEAKAGE REDUCTION; POWER GATING;

LEAKAGE CURRENTS;

EID: 33947149666     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.859560     Document Type: Article

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