메뉴 건너뛰기




Volumn , Issue , 2002, Pages 108-116

Increasing power efficiency of multi-core network processors through data filtering

Author keywords

Chip multiprocessors; Data locality; Network processors; Power reduction; Remote procedure call

Indexed keywords

CHIP MULTIPROCESSOR; DATA LOCALITY; NETWORK PROCESSOR; POWER REDUCTIONS; REMOTE PROCEDURE CALL;

EID: 77953016638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581647     Document Type: Conference Paper
Times cited : (9)

References (28)
  • 8
    • 0031096193 scopus 로고    scopus 로고
    • A Case for Intelligent RAM: IRAM
    • April
    • D. Patterson, et al., A Case for Intelligent RAM: IRAM, in IEEE Micro. April 1997.
    • (1997) IEEE Micro
    • Patterson, D.1
  • 10
    • 0030243819 scopus 로고    scopus 로고
    • Energy dissipation in general purpose microprocessors
    • PII S0018920096064773
    • Gonzalez, R. and M. Horowitz, Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 1996. 31(9): p. 1277-1284 (Pubitemid 126576632)
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.9 , pp. 1277-1283
    • Gonzalez, R.1    Horowitz, M.2
  • 11
    • 0003220329 scopus 로고    scopus 로고
    • Intel Network Processor Targets Routers
    • Sep. 13
    • Halfhill, T. R., Intel Network Processor Targets Routers, in Microprocessor Report. Sep. 13, 1999.
    • (1999) Microprocessor Report
    • Halfhill, T.R.1
  • 14
    • 85133561916 scopus 로고    scopus 로고
    • Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers
    • Jouppi, N. P. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. In Proceedings of 25 Years {ISCA}: Retrospectives and Reprints, 388-397, 1998.
    • (1998) Proceedings of 25 Years {ISCA}: Retrospectives and Reprints , pp. 388-397
    • Jouppi, N.P.1
  • 21
    • 0030285348 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
    • Montanaro, J., et al., A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 1996. 31(11): p. 1703-1714
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.11 , pp. 1703-1714
    • Montanaro, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.