-
1
-
-
0028055525
-
Predictability of Load/Store Instruction Latencies
-
Abraham, S. G., R. A. Sugumar, D. Windheiser, B. R. Rau, and R. Gupta. Predictability of Load/Store Instruction Latencies. In Proceedings of Twenty-sixth International Symposium on Microarchitecture (MICRO-26), Dec. 1993.
-
Proceedings of Twenty-sixth International Symposium on Microarchitecture (MICRO-26), Dec. 1993
-
-
Abraham, S.G.1
Sugumar, R.A.2
Windheiser, D.3
Rau, B.R.4
Gupta, R.5
-
3
-
-
0028573831
-
Towards a Programming Environment for a Computer with Intelligent Memory
-
Asthana, A., M. Cravatts, and P. Krzyzanowski. Towards a Programming Environment for a Computer with Intelligent Memory. In Proceedings of Proc. of the Parallel Architectures and Compilation Techniques, Aug. 1994, Montreal / Canada.
-
Proceedings of Proc. of the Parallel Architectures and Compilation Techniques, Aug. 1994, Montreal / Canada
-
-
Asthana, A.1
Cravatts, M.2
Krzyzanowski, P.3
-
4
-
-
0031642231
-
Power and Performance Tradeoffs using Various Caching Strategies
-
Bahar, R. I., G. Albera, and S. Manne. Power and Performance Tradeoffs using Various Caching Strategies. In Proceedings of International Symposium on Low Power Electronics and Design, Aug. 1998, Monterey / CA.
-
Proceedings of International Symposium on Low Power Electronics and Design, Aug. 1998, Monterey / CA
-
-
Bahar, R.I.1
Albera, G.2
Manne, S.3
-
5
-
-
0031619877
-
Architectural and compiler support for energy reduction in the memory hierarchy of high performance processors
-
Bellas, N., I. Hajj, C. Polychronopoulos, and G. Stamoulis. Architectural and compiler support for energy reduction in the memory hierarchy of high performance processors. In Proceedings of Intl. Symposium on Low Power Electronics and Design, Aug. 1998.
-
Proceedings of Intl. Symposium on Low Power Electronics and Design, Aug. 1998
-
-
Bellas, N.1
Hajj, I.2
Polychronopoulos, C.3
Stamoulis, G.4
-
8
-
-
0031096193
-
A Case for Intelligent RAM: IRAM
-
April
-
D. Patterson, et al., A Case for Intelligent RAM: IRAM, in IEEE Micro. April 1997.
-
(1997)
IEEE Micro
-
-
Patterson, D.1
-
10
-
-
0030243819
-
Energy dissipation in general purpose microprocessors
-
PII S0018920096064773
-
Gonzalez, R. and M. Horowitz, Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 1996. 31(9): p. 1277-1284 (Pubitemid 126576632)
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.9
, pp. 1277-1283
-
-
Gonzalez, R.1
Horowitz, M.2
-
11
-
-
0003220329
-
Intel Network Processor Targets Routers
-
Sep. 13
-
Halfhill, T. R., Intel Network Processor Targets Routers, in Microprocessor Report. Sep. 13, 1999.
-
(1999)
Microprocessor Report
-
-
Halfhill, T.R.1
-
14
-
-
85133561916
-
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers
-
Jouppi, N. P. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. In Proceedings of 25 Years {ISCA}: Retrospectives and Reprints, 388-397, 1998.
-
(1998)
Proceedings of 25 Years {ISCA}: Retrospectives and Reprints
, pp. 388-397
-
-
Jouppi, N.P.1
-
15
-
-
0031336708
-
The Filter Cache: An energy efficient memory structure
-
Kin, J., M. Gupta, and W. H. Mangione-Smith. The Filter Cache: an energy efficient memory structure. In Proceedings of Intl. Symposium on Microarchitecture, Dec. 1997, Research Triangle Park / NC.
-
Proceedings of Intl. Symposium on Microarchitecture, Dec. 1997, Research Triangle Park / NC
-
-
Kin, J.1
Gupta, M.2
Mangione-Smith, W.H.3
-
16
-
-
84870766462
-
Combined DRAM and Logic Chip for Massively Parallel Applications
-
Kogge, P. M., T. Sunaga, E. Retter, et al. Combined DRAM and Logic Chip for Massively Parallel Applications. In Proceedings of 16th IEEE Conference on Advanced Research in VLSI, March 1995, Raleigh / NC.
-
Proceedings of 16th IEEE Conference on Advanced Research in VLSI, March 1995, Raleigh / NC
-
-
Kogge, P.M.1
Sunaga, T.2
Retter, E.3
-
19
-
-
0032121748
-
Smarter Memory: Improving Bandwidth for Streamed References
-
July
-
McKee, S. A., R. H. Klenke, K. L. Wright, W. A. Wulf, M. H. Salinas, J. H. Aylor, and A.P. Batson, Smarter Memory: Improving Bandwidth for Streamed References, in IEEE Computer. July 1998. p. 54-63.
-
(1998)
IEEE Computer
, pp. 54-63
-
-
McKee, S.A.1
Klenke, R.H.2
Wright, K.L.3
Wulf, W.A.4
Salinas, M.H.5
Aylor, J.H.6
Batson, A.P.7
-
20
-
-
0035215332
-
NetBench: A Benchmarking Suite for Network Processors
-
Nov. San Jose / CA
-
Memik, G., W. H. Mangione-Smith, and W. Hu. NetBench: A Benchmarking Suite for Network Processors. In Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 39-42, Nov. 2001, San Jose / CA.
-
(2001)
Proceedings of International Conference on Computer-Aided Design (ICCAD)
, pp. 39-42
-
-
Memik, G.1
Mangione-Smith, W.H.2
Hu, W.3
-
21
-
-
0030285348
-
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
-
Montanaro, J., et al., A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 1996. 31(11): p. 1703-1714
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montanaro, J.1
-
22
-
-
84943181195
-
JETTY: Snoop filtering for reduced power in SMP servers
-
Moshovos, A., G. Memik, B. Falsafi, and A. Choudhary. JETTY: Snoop filtering for reduced power in SMP servers. In Proceedings of International Symposium on High Performance Computer Architecture (HPCA-7), Jan 2001, Toulouse / France.
-
Proceedings of International Symposium on High Performance Computer Architecture (HPCA-7), Jan 2001 Toulouse / France
-
-
Moshovos, A.1
Memik, G.2
Falsafi, B.3
Choudhary, A.4
-
24
-
-
0033645390
-
Gated-Vdd: A circuit technique to reduce leakage in cache memories
-
Powell, M. D., S. H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar. Gated-Vdd: A circuit technique to reduce leakage in cache memories. In Proceedings of Intl. Symposium on Low Power Electronics and Design, July 2000.
-
Proceedings of Intl. Symposium on Low Power Electronics and Design, July 2000
-
-
Powell, M.D.1
Yang, S.H.2
Falsafi, B.3
Roy, K.4
Vijaykumar, T.N.5
-
26
-
-
0031164362
-
Managing data caches using selective cache line replacement
-
Tyson, G., M. Farrens, J. Matthews, and A. R. Pleszkun, Managing Data Caches Using Selective Cache Line Replacement. International Journal of Parallel Programming, 1997. 25(3): p. 213-242. (Pubitemid 127818259)
-
(1997)
International Journal of Parallel Programming
, vol.25
, Issue.3
, pp. 213-242
-
-
Tyson, G.1
Farrens, M.2
Matthews, J.3
Pleszkun, A.R.4
|