Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 25, Issue 1, 2017, Pages 210-223

  Azarkhish, Erfan ^a   Pfister, Christoph ^b   Rossi, Davide ^a   Loi, Igor ^a   Benini, Luca ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b ETH ZURICH   (Switzerland)

Author keywords

3 D integration; address scrambling; cycle accurate (CA) model; interconnect design; smart memory cube (SMC)

Indexed keywords

BANDWIDTH; COMPUTATION THEORY; DESIGN; ELECTRIC POWER UTILIZATION; GEOMETRY; INTEGRATED CIRCUIT DESIGN; LOGIC DESIGN; LOGIC SYNTHESIS; RECONFIGURABLE HARDWARE;

ADDRESSING SCHEME; BACKWARD COMPATIBLE; CYCLE-ACCURATE SIMULATION; GENERIC PROCESSORS; INTERCONNECT DESIGN; MEMORY COMPUTATIONS; REAL APPLICATIONS; ROBUST OPERATION;

COMPUTER CIRCUITS;

EID: 84973573025     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2016.2570283     Document Type: Article

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