Return data interleaving for multi-channel embedded CMPs systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 7, 2012, Pages 1351-1354

  Hong, Fei ^a   Shrivastava, Aviral ^a   Lee, Jongeun ^b  

^a ARIZONA STATE UNIVERSITY   (United States)

^b Ulsan National Institute of Science and Technology   (South Korea)

Author keywords

Chip multi core processor; multi channel memory; return data interleaving (RDI)

Indexed keywords

CHIP MULTI CORES; EXECUTION TIME; MEMORY BANDWIDTHS; MEMORY CONTROLLER; MEMORY SUBSYSTEMS; MULTI-CHANNEL; RETURN DATA INTERLEAVING (RDI); ROUND ROBIN; SCHEDULING POLICIES; VOLUME MEMORY;

BENCHMARKING; BUSES; COMPUTER SIMULATION;

EMBEDDED SYSTEMS;

EID: 84862233003     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2157368     Document Type: Article

References (21)

1. ITRS, "International Technology Roadmap for Semiconductors: Executive Summary," 2005.
2. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The m5 simulator: Modeling networked systems," IEEE Micro, vol. 26, pp. 52-60, 2006. (Pubitemid 46504889)
3. L. T. Clark, E. J. Hoffman, J. Miller, M. Biyani, Y. Liao, S. Strazdus, M. Morrow, K. E. Velarde, and M. A. Yarch, "An embedded 32-b microprocessor core for low-power and high-performance applications," IEEE J. Solid-States Circuits, vol. 36, no. 11, pp. 1599-1608, Nov. 2001. (Pubitemid 33105923)
4. Q. S. Gao, "The Chinese remainder theorem and the prime memory system," in Proc. 20th Annu. Int. Symp. Comput. Arch. (ISCA), 1993, pp. 337-340. (Pubitemid 23675547)
5. I. Hur and C. Lin, "Memory scheduling for modern microprocessors," ACM Trans. Comput. Syst., vol. 25, 2007.
6. W.-F. Lin, "Reducing dram latencies with an integrated memory hierarchy design," in Proc. 7th Int. Symp. High-Perform. Comput. Arch. (HPCA), 2001, p. 301.
7. S. G. Lloyd, "Burst mode cache with wrap-Around fill," U.S. Patent No. 4 912 631, Mar. 27, 1990.
8. B. K. Mathew, S. A. McKee, J. B. Carter, and A. Davis, "Algorithmic foundations for a parallel vector access memory system," in Proc. 12th Annu. ACM Symp. Parallel Algorithms Arch. (SPAA), 2000, pp. 156-165.
9. S. A. McKee, "Maximizing memory bandwidth for streamed computations," Ph.D. dissertation, Dept. Comput. Sci., Univ. Virginia, Charlottesville, VA, 1995.
10. S. A. Mckee, S. A. Mckee, and S. A. Mckee, "Hardware support for dynamic access ordering: Performance of some design options," 1993.
11. S. A. McKee, W. A.Wulf, J. H. Aylor, M. H. Salinas, R. H. Klenke, S. I. Hong, and D. A. B. Weikle, "Dynamic access ordering for streamed computations," IEEE Trans. Comput., vol. 49, no. 11, pp. 1255-1271, Nov. 2000. (Pubitemid 32076240)
12. S. A. Moyer, "Access ordering and effective memory bandwidth," Ph.D. dissertation, Dept. Comput. Sci., Univ. Virginia, Charlottesville, VA, 1993.
13. C. Natarajan, B. Christenson, and F. Briggs, "A study of performance impact of memory controller features in multi-processor server environment," in Proc. 3rd Workshop Memory Perform. Issues (WMPI), 2004, pp. 80-87.
14. M. Peiron, M. Valero, E. Ayguadé, and T. Lang, "Vector multiprocessors with arbitrated memory access," SIGARCH Comput. Arch. News, vol. 23, no. 2, pp. 243-252, 1995.
15. R. Raghavan and J. P. Hayes, "On randomly interleaved memories," in Proc. ACM/IEEE Conf. Supercomput. (Supercomputing), 1990, pp. 49-58.
16. B. R. Rau, "Pseudo-randomly interleaved memory," SIGARCH Comput. Archit. News, vol. 19, no. 3, pp. 74-83, 1991. (Pubitemid 21690872)
17. B. M. Sally, S. A. Mckee, J. B. Carter, and A. Davis, "Design of a parallel vector access unit for SDRAM memory systems," in Proc. 6th Annu. Symp. High Perform. Comput. Arch., 2000, pp. 39-48. (Pubitemid 34197747)
18. L. Spracklen and S. G. Abraham, "Chip multithreading: Opportunities and challenges," in Proc. 11th Int. Conf. High-Perform. Comput. Arch. (HPCA-11), 2005, pp. 248-252.
19. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel, and B. Jacob, "DRAMsim: A memory system simulator," ACM SIGARCH Comput. Arch. News, vol. 33, no. 4, pp. 100-107, Sep. 2005.
20. D. T. Wang, "Modern drammemory systems: Performance analysis and scheduling algorithm," Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. Maryland, College Park, MD, 2005.
21. W. A. Wulf and S. A. Mckee, "Hitting the memory wall: Implications of the obvious," Comput. Arch. News, vol. 23, pp. 20-24, 1995.