A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects

IET Computers and Digital Techniques

Volumn 7, Issue 5, 2013, Pages 191-199

  Azarkhish, Erfan ^a   Loi, Igor ^a   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL ELEMENT; ARCHITECTURAL SIMULATION; ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS; MANUFACTURING COST; MEMORY CONFIGURATION; MULTI-CORE CLUSTER; PROCESSING ELEMENTS; THROUGH-SILICON-VIA;

CLOSED LOOP CONTROL SYSTEMS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE;

THREE DIMENSIONAL;

EID: 84883288792     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2013.0031     Document Type: Article

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