A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 230-231

  Hamzaoglu, Fatih ^a   Arslan, Umut ^a   Bisnik, Nabhendra ^a   Ghosh, Swaroop ^a   Lal, Manoj B ^a   Lindert, Nick ^a   Meterelliyoz, Mesut ^a   Osborne, Randy B ^a   Park, Joodong ^a   Tomishima, Shigeki ^a   Wang, Yih ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

CMOS TECHNOLOGY; DESIGN FEATURES; HIGH BANDWIDTH; LOGIC TECHNOLOGY; LOW-POWER LOGIC; OPERATING VOLTAGE; PERFORMANCE GAPS; TRI-GATE TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84898063371     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757412     Document Type: Conference Paper

References (7)

1. J. Barth et al., "A 45nm SOI Embedded DRAM Macro for POWER7™ 32MB On-Chip L3 Cache", ISSCC Dig. Tech. Papers, pp. 342-344, Feb. 2010.
2. K. Hijioka et al., "A Novel Cylinder-Type MIM Capacitor in Porous Low-k Film (CAPL) for Embedded DRAM with Advanced CMOS Logics," IEDM Technical Digest, pp. 756-759, Dec. 2010.
3. S. Romanovsky et al., "A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS", ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2008.
4. R. Brain et al., "A 22nm High Performance Embedded DRAM SoC Technology Featuring Tri-Gate Transistors and MIMCAP COB", VLSI Tech. Symp., June 2013.
5. N. Kurd et al., "Haswell: A Family of IA 22nm Processors," ISSCC Dig. Tech. Papers, Feb. 2014
6. Y. Wang et al., "Retention Time Optimization for eDRAM in 22nm Tri-Gate CMOS Technology," IEDM Technical Digest, Dec. 2013.
7. E. Karl et al., "A 4.6GHz, 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active Vmin-Enhancing Assist Circuitry," ISSCC Dig. Tech. Papers, pp. 230-232, Feb. 2012.