DRAMA: An architecture for accelerated processing near memory

IEEE Computer Architecture Letters

Volumn 14, Issue 1, 2015, Pages 26-29

  Farmahini Farahani, Amin ^a   Ahn, Jung Ho ^b   Morrow, Katherine ^a   Kim, Nam Sung ^a  

^a University of Wisconsin Madison   (United States)

^b Seoul National University   (South Korea)

Author keywords

3D stacking; accelerator; DRAM; energy efficient computing; Near memory processing

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; DATA TRANSFER; DIGITAL STORAGE; DYNAMIC RANDOM ACCESS STORAGE; ELECTRONICS PACKAGING; ENERGY EFFICIENCY; ENERGY UTILIZATION; IMAGE CODING; INTEGRATED CIRCUIT INTERCONNECTS; MEMORY ARCHITECTURE; PARTICLE ACCELERATORS; RECONFIGURABLE ARCHITECTURES;

3D STACKING; COARSE-GRAIN RECONFIGURABLE; COMMODITY PROCESSORS; ENERGY EFFICIENT COMPUTING; HIGH PERFORMANCE COMPUTING SYSTEMS; MEMORY HIERARCHY; PROCESSING UNITS; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84932635177     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/LCA.2014.2333735     Document Type: Article

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