Data Allocation for Hybrid Memory with Genetic Algorithm

IEEE Transactions on Emerging Topics in Computing

Volumn 3, Issue 4, 2015, Pages 544-555

  Qiu, Meikang ^a,b   Chen, Zhi ^c   Niu, Jianwei ^d   Zong, Ziliang ^e   Quan, Gang ^f   Qin, Xiao ^g   Yang, Laurence T ^a,h  

^a HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^b PACE UNIVERSITY   (United States)

^c UNIVERSITY OF KENTUCKY   (United States)

^d BEIHANG UNIVERSITY   (China)

^e Texas State University San Marcos   (United States)

^f Florida International University   (United States)

^g AUBURN UNIVERSITY   (United States)

^h ST FRANCIS XAVIER UNIVERSITY   (Canada)

Author keywords

chip multiprocessor; data allocation; genetic algorithm; Hybrid memory; MRAM; SPM; Z RAM

Indexed keywords

ALGORITHMS; BUDGET CONTROL; GENETIC ALGORITHMS; MAGNETIC RECORDING; MAGNETIC STORAGE; MRAM DEVICES; MULTIPROCESSING SYSTEMS; RANDOM ACCESS STORAGE; STATIC RANDOM ACCESS STORAGE;

CHIP MULTIPROCESSOR; CRITICAL CHALLENGES; DATA ALLOCATION; HYBRID MEMORY; MEMORY ACCESS; MEMORY SYSTEMS; MRAM; ON CHIP MEMORY;

MEMORY ARCHITECTURE;

EID: 84961680247     PISSN: None     EISSN: 21686750     Source Type: Journal    
DOI: 10.1109/TETC.2015.2398824     Document Type: Article

References (27)

1. J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," Digit. Tech. J., vol. 9, no. 1, pp. 49-62, 1997.
2. M. Qiu, Z. Chen, and M. Liu, "Low-power low-latency data allocation for hybrid scratch-pad memory," IEEE Embedded Syst. Lett., vol. 6, no. 4, pp. 69-72, Dec. 2014.
3. M. Qiu, Z. Chen, Z. Ming, X. Qin, and J. W. Niu, "Energy-aware data allocation for mobile cloud systems," IEEE Syst. J., doi: 10.1109/JSYST.2014.2345733.
4. R. Banakar, S. Steinke, B.-S. Lee, M. Balakrishnan, and R. Marwedel, "Scratchpad memory: A design alternative for cache on-chip mem-ory in embedded systems," in Proc. 10th Int. Symp. Hardw./Softw. Codesign (CODES), May 2002, pp. 73-78.
5. P. R. Panda, N. D. Dutt, and A. Nicolau, "Efficient utilization of scratch-pad memory in embedded processor applications," in Proc. Eur. Design Test Conf., Mar. 1997, pp. 7-11.
6. C. R. Johns and D. A. Brokenshire, "Introduction to the cell broadband engine architecture," IBM J. Res. Develop., vol. 51, no. 5, pp. 503-519, Sep. 2007.
7. S. Udayakumaran and R. Barua, "Compiler-decided dynamic mem-ory allocation for scratch-pad based embedded systems," in Proc. Int. Conf. Compil., Archit. Synthesis Embedded Syst. (CASES), Oct. 2003, pp. 276-286.
8. G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, "A novel architecture of the 3D stacked MRAM L2 cache for CMPs," in Proc. 36th Annu. Int. Symp. Comput. Archit. (ISCA), Feb. 2009, pp. 239-249.
9. J. Hu, C. J. Xue, Q. Zhuge, W.-C. Tseng, and E. H.-M. Sha, "Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory," in Proc. Design, Autom. Test Eur. Conf. Exhibit. (DATE), Mar. 2011, pp. 1-6.
10. D. Whitley, "A genetic algorithm tutorial," Statist. Comput., vol. 4, no. 2, pp. 65-85, Jun. 1994.
11. V. Suhendra, A. Roychoudhury, and T. Mitra, "Scratchpad allocation for concurrent embedded software," ACM Trans. Program. Lang. Syst., vol. 32, no. 4, pp. 13:1-13:47, 2010.
12. J. Whitham, R. I. Davis, N. C. Audsley, S. Altmeyer, and C. Maiza, "Investigation of scratchpad memory for preemptive multitasking," in Proc. 33rd IEEE Int. Real-Time Syst. Symp. (RTSS), San Juan, PR, USA, Dec. 2012, pp. 3-13.
13. J. Whitham and N. Audsley, "The scratchpad memory management unit for microblaze: Implementation, testing, and case study," Dept. Comput. Sci., Univ. York, Heslington, U.K., Tech. Rep. YCS-2009-439, 2009.
14. N. Nguyen, A. Dominguez, and R. Barua, "Memory allocation for embed-ded systems with a compile-time-unknown scratch-pad size," in Proc. Int. Conf. Compil., Archit. Synthesis Embedded Syst. (CASES), San Francisco, CA, USA, Sep. 2005, pp. 115-125.
15. A. Dominguez, S. Udayakumaran, and R. Barua, "Heap data allocation to scratch-pad memory in embedded systems," J. Embedded Comput., vol. 1, no. 4, pp. 521-540, Dec. 2005.
16. B. Egger, J. Lee, and H. Shin, "Dynamic scratchpad memory management for code in portable systems with an MMU," ACM Trans. Embedded Comput. Syst., vol. 7, no. 2, pp. 11:1-11:38, Feb. 2008.
17. Y. Guo, Q. Zhuge, J. Hu, M. Qiu, and E. H.-M. Sha, "Optimal data allocation for scratch-pad memory on embedded multi-core systems," in Proc. 40th Int. Conf. Parallel Process. (ICPP), Taipei, Taiwan, Sep. 2011, pp. 464-471.
18. S. Udayakumaran, A. Dominguez, and R. Barua, "Dynamic allocation for scratch-pad memory using compile-time decisions," ACM Trans. Embedded Comput. Syst., vol. 5, no. 2, pp. 472-511, May 2006.
19. J. Hu, C. J. Xue, Q. Zhuge, W.-C. Tseng, and E. H. Sha, "Data allocation optimization for hybrid scratch pad memory with SRAM and nonvolatile memory," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 6, pp. 1094-1102, Jun. 2012.
20. J. Hu, Q. Zhuge, C. J. Xue,W.-C. Tseng, and E. H.-M. Sha, "Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors," ACM Trans. Embedded Comput. Syst., vol. 13, no. 4, Nov. 2014, Art. ID 79.
21. H. P. Hofstee, "Power efficient processor architecture and the cell processor," in Proc. IEEE 11th Int. Symp. High Perform. Comput. Archit. (HPCA), Feb. 2005, pp. 258-262.
22. E. S. H. Hou, N. Ansari, and H. Ren, "A genetic algorithm for multi-processor scheduling," IEEE Trans. Parallel Distrib. Syst., vol. 5, no. 2, pp. 113-120, Feb. 1994.
23. M. Srinivas and L. M. Patnaik, "Adaptive probabilities of crossover and mutation in genetic algorithms," IEEE Trans. Syst., Man, Cybern., vol. 24, no. 4, pp. 656-667, Apr. 1994.
24. K. Shahookar and P. Mazumder, "A genetic approach to standard cell placement using meta-genetic parameter optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 9, no. 5, pp. 500-511, May 1990.
25. Parsec. [Online]. Available: http://parsec.cs.princeton.edu/, accessed 2010.
26. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The M5 simulator: Modeling networked systems," IEEE Micro, vol. 26, no. 4, pp. 52-60, Jul./Aug. 2006.
27. N. Muralimanohar, R. Balasubramonian, and N. Jouppi, "Optimiz-ing NUCA organizations and wiring alternatives for large caches with CACTI 6.0," in Proc. 40th Annu. IEEE/ACM Int. Symp., Dec. 2007, pp. 3-14.