Low-power low-latency data allocation for hybrid scratch-pad memory

IEEE Embedded Systems Letters

Volumn 6, Issue 4, 2014, Pages 69-72

  Qiu, Meikang ^a   Chen, Zhi ^b   Liu, Meiqin ^c  

^a PACE UNIVERSITY   (United States)

^b UNIVERSITY OF KENTUCKY   (United States)

^c ZHEJIANG UNIVERSITY   (China)

Author keywords

Data allocation; dynamic programming; genetic algorithm; hybrid memory; multicore; scratch pad memory (SPM)

Indexed keywords

ALGORITHMS; CODE CONVERTERS; DYNAMIC PROGRAMMING; EMBEDDED SYSTEMS; GENETIC ALGORITHMS; MEMORY ARCHITECTURE; MULTICORE PROGRAMMING; STATIC RANDOM ACCESS STORAGE;

DATA ALLOCATION; HYBRID MEMORY; MEMORY ACCESS; MEMORY BANKS; MEMORY WALL; MULTI CORE; MULTI-CORE EMBEDDED SYSTEMS; SCRATCH PAD MEMORY;

MRAM DEVICES;

EID: 84913543588     PISSN: 19430663     EISSN: None     Source Type: Journal    
DOI: 10.1109/LES.2014.2344913     Document Type: Article

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