SCOPUS 정보 검색 플랫폼

Eurasip Journal on Embedded Systems

Volumn 2006, Issue , 2006, Pages

NoC design flow for TDMA and QoS management in a GALS context

(3) Evain, Samuel a Diguet, Jean Philippe a Houzet, Dominique b

a UNIVERSITÉ DE BRETAGNE SUD (France)

b CNRS (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33751521824 PISSN: 16873955 EISSN: 16873963 Source Type: Journal
DOI: 10.1155/ES/2006/63656 Document Type: Article

Times cited : (15)

References (17)

1
- 0034848112
- Route packets, not wires: On-chip interconnection networks
- Las Vegas, Nev, USA
- W. J. Dally B. Towles Route packets, not wires: on-chip interconnection networks. Proceedings of the 38th Design Automation Conference (DAC '01) Las Vegas, Nev, USA 2001 684 689
- (2001) Proceedings of the 38th Design Automation Conference (DAC '01) , pp. 684-689
- Dally, W.J.¹ Towles, B.²

2
- 79955158088
- Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs
- Montpellier, France
- T. Marescaux A. Bartic D. Verkest S. Vernalde R. Lauwereins Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs. Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02) Montpellier, France 2002 795 805
- (2002) Proceedings of the 12th International Conference on Field-Programmable Logic and Applications (FPL '02) , pp. 795-805
- Marescaux, T.¹ Bartic, A.² Verkest, D.³ Vernalde, S.⁴ Lauwereins, R.⁵

3
- 33749054084
- Interconnect-limited VLSI architecture
- San Francisco, Calif, USA
- W. J. Dally Interconnect-limited VLSI architecture. Proceedings of IEEE International Conference Interconnect Technology San Francisco, Calif, USA 1999 15 17
- (1999) Proceedings of IEEE International Conference Interconnect Technology , pp. 15-17
- Dally, W.J.¹

4
- 33846963139
- From NoC security analysis to design solutions
- Athens, Greece
- S. Evain J.-Ph. Diguet From NoC security analysis to design solutions. Proceedings of The IEEE Workshop on Signal Processing Systems (SIPS '05) Athens, Greece 2005
- (2005) Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS '05)
- Evain, S.¹ Diguet, J.-Ph.²

5
- 0026825968
- Virtual-channel flow control
- W. J. Dally Virtual-channel flow control. IEEE Transactions on Parallel and Distributed Systems 3 2 1992 194 205
- (1992) IEEE Transactions on Parallel and Distributed Systems , vol.3 , Issue.2 , pp. 194-205
- Dally, W.J.¹

6
- 27644469931
- Automatic hardware-efficient SoC integration by QoS network on chip
- Tel-Aviv, Israel
- E. Bolotin A. Morgenshtein I. Cidon R. Ginosar A. Kolodny Automatic hardware-efficient SoC integration by QoS network on chip. Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS∼'04) Tel-Aviv, Israel 2004 479 482
- (2004) Proceedings of the 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS∼'04) , pp. 479-482
- Bolotin, E.¹ Morgenshtein, A.² Cidon, I.³ Ginosar, R.⁴ Kolodny, A.⁵

7
- 0042534136
- Guaranteeing the quality of services in networks on chip
- Kluwer Academic Dordrecht, The Netherlands
- K. Goossens J. Dielissen J. van Meerbergen A. Jantsch H. Tenhunen Guaranteeing the quality of services in networks on chip. Networks on Chip Kluwer Academic Dordrecht, The Netherlands 2003 61 82
- (2003) Networks on Chip , pp. 61-82
- Goossens, K.¹ Dielissen, J.² Van Meerbergen, J.³ Jantsch, A.⁴ Tenhunen, H.⁵

8
- 3042740415
- Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
- thid@imit.kth.se erlandn@imit.kth.se micke@imit.kth.se axel@imit.kth.se Paris, France
- M. Millberg micke@imit.kth.se E. Nilsson erlandn@imit.kth.se R. Thid thid@imit.kth.se A. Jantsch axel@imit.kth.se Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip. Proceedings of Design, Automation and Test in Europe (DATE '04) Paris, France 2 2004 890 895
- (2004) Proceedings of Design, Automation and Test in Europe (DATE '04) , vol.2 , pp. 890-895
- Millberg, M.¹ Nilsson, E.² Thid, R.³ Jantsch, A.⁴

9
- 0036761284
- Coping with latency in SOC design
- lcarloni@ic.eecs.berkeley.edu. special issue on systems on chip
- L. P. Carloni lcarloni@ic.eecs.berkeley.edu A. L. Sangiovanni-Vincentelli Coping with latency in SOC design. IEEE Micro 22 5 2002 24 35 special issue on systems on chip
- (2002) IEEE Micro , vol.22 , Issue.5 , pp. 24-35
- Carloni, L.P.¹ Sangiovanni-Vincentelli, A.L.²

10
- 84881243015
- Nexus: An asynchronous crossbar interconnect for synchronous system-on-chip designs
- Stanford, Calif, USA
- A. Lines Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. Proceedings of the 11th Symposium on High Performance Interconnects Stanford, Calif, USA 2003 2 9
- (2003) Proceedings of the 11th Symposium on High Performance Interconnects , pp. 2-9
- Lines, A.¹

11
- 33751528316
- Arteris
- Arteris, http://www.arteris.net

12
- 28444486004
- An asynchronous NOC architecture providing low latency service and its multi-level design framework
- alain.clouard@st.com pascal.vivet@cea.fr fabien.clermidy@cea.fr edith.beigne@cea.fr marc.renaudin@imag.fr New York, NY, USA
- E. Beigné edith.beigne@cea.fr F. Clermidy fabien.clermidy@cea.fr P. Vivet pascal.vivet@cea.fr A. Clouard alain.clouard@st.com M. Renaudin marc.renaudin@imag.fr An asynchronous NOC architecture providing low latency service and its multi-level design framework. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05) New York, NY, USA 2005 54 63
- (2005) Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05) , pp. 54-63
- Beigné, E.¹ Clermidy, F.² Vivet, P.³ Clouard, A.⁴ Renaudin, M.⁵

13
- 28444450874
- A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip
- tob@imm.dtu.dk jsp@imm.dtu.dk New York, NY, USA
- T. Bjerregaard tob@imm.dtu.dk J. Sparsø jsp@imm.dtu.dk A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05) New York, NY, USA 2005 34 43
- (2005) Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '05) , pp. 34-43
- Bjerregaard, T.¹ Sparsø, J.²

14
- 33646939836
- Using mobilize power management IP for dynamic & static power reduction in SoC at 130 nm
- danh@virtual-silicon.com Munich, Germany
- D. Hillman danh@virtual-silicon.com Using mobilize power management IP for dynamic & static power reduction in SoC at 130 nm. Proceedings of Design, Automation and Test in Europe (DATE '05) Munich, Germany 3 2005 240 246
- (2005) Proceedings of Design, Automation and Test in Europe (DATE '05) , vol.3 , pp. 240-246
- Hillman, D.¹

15
- 84893753441
- Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
- Munich, Germany
- E. Rijpkema K. Goossens A. Rdulescu Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip. Proceedings of Design Automation and Test Conference in Europe (DATE '03) Munich, Germany 2003 350 355
- (2003) Proceedings of Design Automation and Test Conference in Europe (DATE '03) , pp. 350-355
- Rijpkema, E.¹ Goossens, K.² Rdulescu, A.³

16
- 3042660381
- An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
- Paris, France
- A. Radulescu J. Dielissen K. Goossens E. Rijpkema P. Wielage An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration. Proceedings of Design, Automation and Test in Europe (DATE '04) Paris, France 2 2004 878 883
- (2004) Proceedings of Design, Automation and Test in Europe (DATE '04) , vol.2 , pp. 878-883
- Radulescu, A.¹ Dielissen, J.² Goossens, K.³ Rijpkema, E.⁴ Wielage, P.⁵

17
- 21444461614
- A generic CAD tool for efficient NoC design
- Seoul, Korea
- S. Evain J.-Ph. Diguet D. Houzet A generic CAD tool for efficient NoC design. Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS '04) Seoul, Korea 2004 728 733
- (2004) Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS '04) , pp. 728-733
- Evain, S.¹ Diguet, J.-Ph.² Houzet, D.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.