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Volumn 15, Issue 2, 2011, Pages 133-158
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Application driven network-on-chip architecture exploration & refinement for a complex SoC
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Author keywords
Architecture exploration; Dynamic memory scheduling; Memory mapped transaction interconnect; Multimedia system on chip (SoC); Network on chip (NoC); Performance verification; Quality of service (QoS); SystemC transaction level modeling (TLM)
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Indexed keywords
ARCHITECTURE EXPLORATION;
DYNAMIC MEMORY SCHEDULING;
MEMORY-MAPPED TRANSACTION INTERCONNECT;
NETWORK ON CHIP;
PERFORMANCE VERIFICATION;
SYSTEM-ON-CHIP;
SYSTEMC;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
COMPUTER ARCHITECTURE;
MULTIMEDIA SYSTEMS;
NETWORK ARCHITECTURE;
QUALITY OF SERVICE;
SERVERS;
VLSI CIRCUITS;
PROGRAMMABLE LOGIC CONTROLLERS;
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EID: 80051666396
PISSN: 09295585
EISSN: 15728080
Source Type: Journal
DOI: 10.1007/s10617-011-9075-5 Document Type: Article |
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Times cited : (42)
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References (0)
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