Using run-time reconfiguration for fault injection in hardware prototypes

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2002-January, Issue , 2002, Pages 245-253

  Antoni, L ^a,b   Leveugle, R ^a   Feher, M ^b  

^a TIMA LABORATORY   (France)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

Circuit faults; Circuit synthesis; Circuit testing; Field programmable gate arrays; Hardware; Laboratories; Power system modeling; Prototypes; Runtime; Single event upset

Indexed keywords

COMPUTER HARDWARE; DEFECTS; DESIGN FOR TESTABILITY; DIGITAL STORAGE; FAULT TOLERANCE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLASH MEMORY; HARDWARE; INTEGRATED CIRCUIT DESIGN; LABORATORIES; LOGIC SYNTHESIS; RADIATION HARDENING; SOFTWARE TESTING; SYNTHESIS (CHEMICAL); VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT SYNTHESIS; CIRCUIT TESTING; POWER SYSTEM MODEL; PROTOTYPES; RUNTIMES; SINGLE EVENT UPSETS;

RECONFIGURABLE HARDWARE;

EID: 84948993581     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.2002.1173521     Document Type: Conference Paper

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