An integrated HW and SW fault injection environment for real-Time systems

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 117-122

  Benso, A ^a   Rebaudengo, M ^a   Reorda, M S ^a   Civera, P L ^b  

^a POLITECNICO DI TORINO   (Italy)

^b Dip Elettronica   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; EMBEDDED SYSTEMS; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; INTERACTIVE COMPUTER SYSTEMS; SOFTWARE TESTING; VLSI CIRCUITS;

AT-SPEED; FAULT INJECTION; LOW COST HARDWARE; SYSTEM BEHAVIORS; TARGET SYSTEMS;

REAL TIME SYSTEMS;

EID: 33746890642     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732158     Document Type: Conference Paper

References (7)

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5. L. T. Young, R. Iyer, K. K. Goswami, A Hybrid Monitor Assisted Fault injection Experiment, Proc. DCCA-3, 1993, pp. 163-174
6. A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A Fault Injection Environment for Microprocessor-based Boards, to be presented to IEEE International Test Conference, Washington (USA), October 1998
7. A. Benso, M. Rebaudengo, L. Impagliazzo, P. Marmo, Fault-list collapsing for fault injection experiments, Proc. Ann. Reliability & Maintainability Symp., 1998, pp. 383-388