Upset-like fault injection in VHDL descriptions: A method and preliminary results

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 259-269

  Velazco, R ^a   Leveugle, R ^a   Calvo, O ^b  

^a TIMA LABORATORY   (France)

^b UNIVERSITAT DE LES ILLES BALEARS   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AVIONICS; CACHE MEMORY; COMPUTER SIMULATION; ERROR ANALYSIS; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; SPACE APPLICATIONS; STATIC RANDOM ACCESS STORAGE;

BIT FLIPS; ERROR RATE ESTIMATION; HIGH-LEVEL CIRCUIT DESCRIPTION; SINGLE EVENT UPSET PHENOMENA; VERY HIGH DEFINITION LANGUAGE;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0035193945     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2001.966778     Document Type: Article

References (12)

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