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IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 242-249

A low-cost hardware approach to dependability validation of IPs

(1) Leveugle, R a

a TIMA LABORATORY (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTERNET; PROBABILITY; SOFTWARE PROTOTYPING;

FAULT INJECTIONS; TRANSIENT FAULTS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035202382 PISSN: 10636722 EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (8)

References (6)

1
- 3743075441
- Emulation based real time testing of automotive applications
- 4th IEEE International On-Line Testing Workshop, Capri, Italy, July 6-8, 1998 , pp. 28-31
- Abke, J.¹ Böhl, E.² Henno, C.³

2
- 33847172128
- Towards modeling for dependability of complex integrated circuits
- 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999 , pp. 194-198
- Leveugle, R.¹

3
- 79960607210
- Real time effect testing of processor faults
- 5th IEEE International On-Line Testing Workshop, Rhodes, Greece, July 5-7, 1999 , pp. 39-43
- Böhl, E.¹ Harter, W.² Trunzer, M.³

4
- 0034517345
- Fault injection in VHDL descriptions and emulation
- IEEE Computer Society Press, Los Alamitos, California, 2000
- The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Yamanashi, Japan, October 25-27, 2000 , pp. 414-419
- Leveugle, R.¹

5
- 0030709784
- Cellular automata for generating deterministic test sequences
- The European Design and Test Conference (ED&TC), 1997 , pp. 77-81
- Kagaris, D.¹ Tragoudas, S.²

6
- 0006767994

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.