Using Run-Time Reconfiguration for fault injection in hardware prototypes

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2000, Pages 405-413

  Antoni, Lörinc ^a,b   Leveugle, Régis ^a   Fehér, Béla ^b  

^a TIMA LABORATORY   (France)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; FAULT TOLERANT COMPUTER SYSTEMS; SOFTWARE PROTOTYPING; RECONFIGURABLE HARDWARE; SOFTWARE TESTING;

FAULT INJECTION; RUN TIME RECONFIGURATION (RTR);

COMPUTER SYSTEM RECOVERY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

FAULT INJECTION; HARDWARE PROTOTYPE; PROGRAMMABLE SYSTEMS; RUN-TIME RECONFIGURATION; RUNTIMES;

EID: 0034501974     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2000.887181     Document Type: Article

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