Fault emulation: A new methodology for fault grading

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 10, 1999, Pages 1487-1495

  Cheng, Kwang Ting ^a,c   Huang, Shi Yu ^a,b   Dai, Wei Jin ^a,b  

^a University of California   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Emulation; Fault grading; Foult simulation; Testing

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; REAL TIME SYSTEMS;

FAULT EMULATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033334585     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.790625     Document Type: Article

References (23)

1. P. Agrawal, V.D. Agrawal, and K.-T. Cheng, "Fault simulation in a pipelined multiprocessor system," in Proc. Int. Test Conf., Aug. 1989, pp. 727-734.
2. L. Burgun, F. Reblewski, G. Fenelon, J. Barbier, and O. Lepape, "Serial fault simulation," in Proc. Design Automation Conf., June 1996, pp. 801-806.
3. M. Abramovici, M.A. Breuer and A.D. Friedman, Digital Systems Testing and Testable Design. Piscataway, NJ: IEEE Press, 1990.
4. M. Butts, J. Batcheller, and J. Varghese, "An efficient logic emulation system," in Proc. Int. Conf. Computer Design (ICCD-92), Oct. 1992, pp. 138-141
5. P.A. Duba, R.K. Roy, J.A. Abraham, and W.A. Rogers, "Fault sim-ulation in a distributed environment," in Proc. 25th Design Automation Conf., June 1988, pp. 686-691.
6. N. Gouders and R. Kaibel, "PARIS: A parallel pattern fault simulator for synchronous sequential circuits," in Proc. Int. Conf. Computer-AidedDesign, Nov. 1991, pp. 542-545.
7. F. Hirose, M. Ishii, J. Niitsuma, T. Shindo, N. Kawato, H. Hamamura, K. Uchida, and H. Yamada, "Simulating processor SP," in Proc. Int. Conf. Computer-Aided Design, Nov. 1987, pp. 484-487.
8. F. Hirose, K. Takayama, and N. Kawato, "A method to generate tests for combinational logic circuits using an ultra high-speed logic simulator," in Proc. Int. Test Conf., 1988, pp. 102-107.
9. V.S. lyengar and D.T. Tang, "On simulation faults in parallel," in Dig. Papers 18th Int. Symp. Fault-Tolerant Computing, June 1988, pp. 110-115.
10. D.H. Lee and S.M. Reddy, "On efficient simulation for synchronous sequential circuits," in Proc. 29th Design Automation Conf., June 1992, pp. 327-331.
11. H.K. Lee and D.S. Ha, "HOPE: An efficient parallel fault simulator for synchronous sequential circuits," in Proc. 29th Design Automation Conf., June 1992, pp. 336-340.
12. _, "New methods of improving parallel fault simulation in synchronous sequential circuits," in Proc. Int. Conf. Conputer-Aided-Design, Nov. 1993, pp. 10-17.
13. C.Y. Lo, H.N. Nham, and A.K. Bose, "Algorithms for an advanced fault simulation system in motis," IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 232-240, Mar. 1987.
14. R. Murgai, N. Shenoy R.K. Brayton, and A. Sagiovanni-Vincentelli, "Improved logic synthesis algorithms for table look up architecture," in Proc. Int. Conf. Computer-Aided Design, Nov. 1991, pp. 564-567.
15. V. Narayanan and V. Pitchumani, "A massively parallel algorithm for fault Simulation on the connection machine," in Proc. 26th Design Automation Conf., June 1989, pp. 734-737.
16. T.M. Niermann, W.T. Cheng, and J.H. Patel, "PROOFS: A fast, memory efficient sequential circuit fault simulator," IEEE Trans. ComputerAided Design, vol. 11, pp. 198-207, Feb. 1992.
17. D.L. Ostapko, Z. Barzilai, and G.M. Silberman, "Fast fault simulation in a parallel processing environment," in Proc. Int. Test Conf., Sept. 1987, pp. 686-691.
18. E.G. Ulrich and T. Baker, "Concurrent simulation of nearly identical digital networks," Computer, pp. 34-44, Apr. 1974.
19. S. Walters, "Computer-aided prototyping for ASIC-based system," IEEE Design Test Comput., pp. 4-10, June 1991.
20. R.W. Wieler, Z. Zhang, and R.D. McLeod, "Simulating static and dynamic faults in BIST structures with a FPGA based emulator," in Proc. Int. Workshop Field-Programmable Logic and Applications, Sept. 1994, pp. 240-250.
21. _, "Emulating static faults using a Xilinx based emulator," in Proc. IEEE Symp. FPGA's for Custom Computing Machines, Feb. 1995, pp. 110-115.
22. "The Programmable Gate Array Data Book," Xilinx Inc., San Jose, CA, 1992.
23. "MARSIII Emulation System User's Guide," Quick-Turn Design System Inc., Mountain View, CA, Jan. 1994.