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1
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84883793672
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2.6 GHz ultra wide voltage range energy efficient dual A9 in 28 nm UTBB FD-SOI
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Proc. VLSI Technology (VLSIT)
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Jacquet, D.1
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79955707786
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A 28 nm 0.6 v low-power DSP for mobile applications
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G. Gammie et al., "A 28 nm 0.6 V low-power DSP for mobile applications," in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 131-134.
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IEEE ISSCC Dig. Tech. Papers
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Gammie, G.1
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3
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84860669777
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A 280 mV-to-1.2 v wide-operating-range IA-32 processor in 32 nm CMOS
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S. Jain et al., "A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 66-68.
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IEEE ISSCC Dig. Tech. Papers
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Jain, S.1
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4
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84860694155
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A 280 mV-to-1.1 v 256 b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS
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S. Hsu et al., "A 280 mV-to-1.1 V 256 b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 178-180.
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Hsu, S.1
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5
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70449707766
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A 45 nm CMOS 0.35 V-optimized standard cell library for ultra-low power applications
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F. Abouzeid et al., "A 45 nm CMOS 0.35 V-optimized standard cell library for ultra-low power applications," in Proc. ISLPED, , 2009, pp. 225-230.
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Proc. ISLPED
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Abouzeid, F.1
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6
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84870778249
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28 nm CMOS, energy efficient and variability tolerant, 350 mV-to-1.0 V, 10 MHz/700 MHz, 252 bits frame error-decoder
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F. Abouzeid, S. Clerc, B. Pelloux-Prayer, F. Argoud, and P. Roche, "28 nm CMOS, energy efficient and variability tolerant, 350 mV-to-1.0 V, 10 MHz/700 MHz, 252 bits frame error-decoder," in Proc. ESSCIRC, 2012, pp. 153-156.
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7
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0034870298
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Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors
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presented at, Huntington Beach, CA, USA, Aug
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J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors," presented at the Int. Symp. Low Power Electronics and Design (ISLPED), Huntington Beach, CA, USA, Aug. 2001.
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The Int. Symp. Low Power Electronics and Design (ISLPED)
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Tschanz, J.1
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De, V.6
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8
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84886725328
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An adaptive pulse-triggered flip-flop for a high-speed and voltage-scalable standard cell library
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Oct
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Luo, S.-C.1
Huang, C.-J.2
Chu, Y.-H.3
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84944408150
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Razor: A low-power pipeline based on circuit-level timing speculation
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presented at, San Diego, CA, USA, Dec
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D. Ernst et al., "Razor: A low-power pipeline based on circuit-level timing speculation," presented at the 36th Annu. IEEE/ACM Int. Symp. Microarchitecture (MICRO-36), San Diego, CA, USA, Dec. 2003.
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Ernst, D.1
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10
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49549105128
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Razor II: In situ error detection and correction for PVT and ser tolerance
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presented at, San Francisco, CA, USA, Feb
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Blaauw, D.1
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Timing error prevention using elastic clocking
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presented at, Kaohsiung, Taiwan, Feb
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K. Chae, C.-H. Lee, and S. Mukhopadhyay, "Timing error prevention using elastic clocking," presented at the IEEE Int. Conf. IC Design & Technology (ICICDT), Kaohsiung, Taiwan, Feb. 2011.
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Chae, K.1
Lee, C.-H.2
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84876139905
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Switching energy efficiency optimization for advanced CPU thanks to UTBB technology
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presented at, San Francisco, CA, USA, Dec
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F. Arnaud, N. Planes, S. Haendler, P. Flatresse, and F. Nyer, "Switching energy efficiency optimization for advanced CPU thanks to UTBB technology," presented at the IEEE Int. Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 2012.
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The IEEE Int. Electron Devices Meeting (IEDM)
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Arnaud, F.1
Planes, N.2
Haendler, S.3
Flatresse, P.4
Nyer, F.5
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2542507417
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High-performance and low-power conditional discharge flip-flop
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May
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Zhao, P.1
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84860655024
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Conditional push-pull pulsed latches with 726fJ.ps energy-delay product in 65nm CMOS
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E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, "Conditional push-pull pulsed latches with 726fJ.ps energy-delay product in 65nm CMOS," in 2012 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2012, pp. 482-484.
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2012 IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers
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Consoli, E.1
Alioto, M.2
Palumbo, G.3
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15
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0035183783
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Timing characterization of dual-edge triggered flip-flops
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N. Nedovic, M. Aleksic, and V. G. Oklobdzija, "Timing characterization of dual-edge triggered flip-flops," in Proc. 2001 Int. Conf. Computer Design, ICCD 2001, pp. 538-541.
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Proc. 2001 Int. Conf. Computer Design, ICCD
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Nedovic, N.1
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