A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 66-67

  Jain, Shailendra ^a   Khare, Surhud ^a   Yada, Satish ^a   Ambili, V ^a   Salihundam, Praveen ^a   Ramani, Shiva ^a   Muthukumar, Sriram ^a   Srinivasan, M ^a   Kumar, Arun ^a   Gb, Shasi Kumar ^a   Ramanarayanan, Rajaraman ^a   Erraguntla, Vasantha ^a   Howard, Jason ^b   Vangal, Sriram ^b   Dighe, Saurabh ^b   Ruhl, Greg ^b   Aseron, Paolo ^b   Wilson, Howard ^b   Borkar, Nitin ^b   De, Vivek ^b   Borkar, Shekhar ^b   more..

^a INTEL TECHNOLOGY INDIA PVT LTD   (India)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CURRENT GENERATION; ENERGY EFFICIENT; SINGLE-THREADED; ULTRALOW VOLTAGE; VOLTAGE RANGES; VOLTAGE-SCALING;

CMOS INTEGRATED CIRCUITS; DEGRADATION;

ENERGY EFFICIENCY;

EID: 84860669777     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6176932     Document Type: Conference Paper

References (4)

1. H. Kaul, et al., "A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS", ISSCC Dig. Tech. Papers, pp. 316-616, 2008.
2. C.H. Jan, et al., "A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications", IEDM Dig. Tech. Papers, pp. 1-4, 2009.
3. J. Schutz, "A 3.3V 0.6um BiCMOS Superscalar Microprocessor", ISSCC Dig. Tech. Papers, pp. 202-203, 1994.
4. A. Wang, et al., "A 180mV FFT Processor using Sub-threshold Circuit Techniques", ISSCC Dig. Tech. Papers, pp. 292-592, 2004.