28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 153-156

  Abouzeid, Fady ^a   Clerc, Sylvain ^a   Pelloux Prayer, Bertrand ^a   Argoud, Fabrice ^a   Roche, Philippe ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK TREE; CMOS TECHNOLOGY; DESIGN EFFORT; DESIGN METHODOLOGY; DIGITAL DESIGNS; ENERGY EFFICIENT; ENERGY REDUCTION; FULLY DEPLETED; STANDARD CELL; ULTRA-WIDE; ULTRALOW VOLTAGE;

CMOS INTEGRATED CIRCUITS; ELECTRIC BATTERIES; ENERGY EFFICIENCY;

DESIGN;

EID: 84870778249     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341282     Document Type: Conference Paper

References (14)

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